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Found 12 results

  1. Hi, I want to read analog data from ad1 pmod. For Vivado part, I use digilent pmod ips to connet fpga. For SDK part, I use AD1.h and AD1.c library in examples. My sensor sends to me analog values between 0-3.3V. (This is a heart rate ECG values). During using arduino, all heart beat data can be read. But I use same function for zedboard, Analog values doesnt look like arduino's. How I can configure and fix this problem? As you see ad1-zedboard connection as below.
  2. Hey all, First off, I apologize - I'm at work, now, with no access to the hardware, o-scope, etc. So all from memory for now, until I can get some time at home.... NOTE: All development being done under Xilinx ISE 14.7 WebPack. Target platform is an Opal Kelly XEM3005 (Xilinx Spartan 3E) Day 1: Wrote & sim'd Verilog to drive a PMODAD1 12b ADC. Seemed to work as planned. Day 2: Tried interfacing to an Opal Kelly XEM3005 (Spartan 3E) board with 3.3V logic & power. No joy. Funky stuff going on. Began troubleshooting. Day 3: Wrote code for Raspberry Pi Zero W (using WiringPi) to drive the AD1. Everything works as it should. Data reads work as close to perfect as I can ask for. Day 4: Continue troubleshooting FPGA - realize my constraints file is no bueno, and is assigning FPGA pins incorrectly. Fixed that. (So, reasonably sure that constraints file is copacetic) Day 5: Wrote code to drive a PMOD DA2 2-channel 12b DAC. Code Sim'd. Works well. Integrated into FPGA - code works well, DA2 works as advertised. Also works well with OK's FrontPanel - I can give a command from the PC, and the DA2 spits out the appropriate voltage. (This was another step to validate FPGA platform functionality & correctness). Day 6: Re-code and re-sim DA1 Verilog. Works as expected. Day 7: Integrate code onto XEM3005 - still no joy. Probe with oscilloscope: Power good - 3.3V, rock solid Ground good: little to no noise. Chip Select (CS) looks good - ~990kHz rate, normally high, Goes low for readout periods. Less than perfect due to being on a protoboard connected via a 6: cable. Serial clock (SCK) looks good - ~16MHz, only active during CS Low periods, high when CS is high (quiet time) DO and D1 outputs - constant low. A fair amount of digital noise. Sometimes, having a probe attached to D0 or D1 with the other probe attached to SCK or CS will couple noise in to the FPGA, giving me a noisy signal that is meaningless (except for the fact that it tells me my inputs are working - or so I think) It appears as though (bare with me - I'm an analog guy) the lines are heavily loaded - i.e., something is pulling the lines to ground. I see on the AD1 datasheet that the outputs are protected by 100 Ohm resistors, so this seems a potential (likely?) culprit (?) Not instantiating IOB's in my code, but those normally aren't necessary except to override defaults in the constraints file. Double- and triple-checked that the D0 and D1 ports are set up as inputs. Constraints file does not explicitly turn on Pull-ups or pull-downs. (LOGIC_3v3, IIRC) Recoded main fixture to move connections to different pins. No change in results - everything (appears) identical. Day 8: Just got home - did some double checking and disconnected the PMOD outputs from the FPGA: With the FPGA disconnected, the signals look pretty darned good: Took some quick measurements of the FPGA input pins - they seem to hava a constant ~0.75V on them with quite a bit of digital trash... This is clearly (I think) an FPGA setup problem.. So, here I am... Looking for clues. Anyone have any? Thanks in advance
  3. Hello, I have recently purchased Zedboard along with Pmods AD1 and DA4. I want to implement Gradient Descent algorithm in the Zedboard using these Pmods with bandwidth more than 100 kHz. To get started, I tried to regenerate a analog signal using the Pmods AD1 and DA4. The experiment is completely explained with block design and output plots in the ADC_DAC_1_compressed.pdf. The SDK C code for acquistion and generation (adc_dac.c) as well as for finding max. working speed of DAC (dac_maxv.c) are atttached. The ADC clk is set to 20 MHz and DAC clk is to 50 MHz. It could be observed from the ADC_DAC_1_compressed.pdf that the maximum speed (frequency) the DAC (DA4) can write is only 33 kHz. The desirable acquisition and generation rate should be more than 200 kHz for my case. I identified that, the Xspi transfer written in the code (adc_dac.c) sends only 8 bits out of 32 bits of the DAC per clock cycle. Can we directly write all the 32 bits of the DAC in a single clk cycle using SDK ?? or is there any other way to make the ADC and DAC work faster?? What am I missing?? Looking forward to you suggestions and other similar references. Thanks in advance
  4. Hello, I have an Analog Discovery (legacy) and the latest Waveforms app. I am trying to write a script that makes the protocol module write to a 24C16 eeprom, read it back, and print to the screen or window. I can access th I2C (can see on my scope), but I can't print anything. The print() function does nothing unless in debug mode, but then the app seems to hang. I tried Custom mode and Sensor mode. And I tried the ADXL345 example, with a known good breakout board, and it always returns the same thing, doesn't change with orientation of the chip (but my main concern is the eeproms) Why is the output window at the bottom of the script area only one line long. The only thing that shows up there is the results of return statements. How can I see the I2C and run the script at the same time ? The logic analyzer only shows the first two I2C bytes, so I'm using an external scope. What does the manual mean when it says the the I2C can only send when in debug ? Isn't that a show-stopper ? Am I missing some key piece of documentation ? The manual does not say much about how all of this stuff works. - Thanks
  5. Waveforms 2015 fails with a segmentation fault whenever I connect an Analog Discovery 1 or an Analog Discovery 2. This happens regardless of whether I connect the AD1/AD2 before starting Waveforms 2015 or while Waveforms 2015 is running. Waveforms 2015 appears to work when no AD1 / AD2 is connected I'm running Ubuntu 16.04.1 on x86-64. I installed: digilent.adept.runtime_2.16.5-amd64.deb digilent.waveforms_3.3.7_amd64.deb "lsusb" output for the AD2: Bus 001 Device 008: ID 0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC "uname" output: $ uname -a Linux 4.4.0-43-generic #63-Ubuntu SMP Wed Oct 12 13:48:03 UTC 2016 x86_64 x86_64 x86_64 GNU/Linux Any suggestions? Thanks, Chris
  6. Hello! I recently purchased the Pmod AD1 for the Zynq Z7-10 and I am trying to sample at 44.1 kHz. How can I set up a clock in the PL for this? Every time I set up a PL fabric clock to a multiple of 44.1 kHz, it is off by maybe ~500 Hz or more. Thank you in advance.
  7. Hello I am new to FPGAs, and I'm using Pmods AD1 and DA2 in a control application on ZedBoard, using VIVADO and SDK. Is there any tutorial or hint to know how to start the design and interfacing between ZedBoard and these pmods. Thanks. Elie.
  8. Hi to all, I was successful in creating working project on Zybo board acquiring voltage using Pmod AD1. It is relatively simple. However the goal is to utilize both channels of the AD1 Pmod. For this I am looking for guidance from experts and community. I might be wrong but it seems that I need to create the second instance of Pmod in Vivado but how do I address the second channel pin D1 and how to initialize the second device. Thank you in advance for any clue I forget to mention that Pmod AD1 definitions were copied from the Digilent vivado-library-master. Update: It appears that all configuration files include both channel pins (2 and 3) of the Pmod AD1. This meand that the second instance of Pmod will not work. The driver seems to be the key. A comment in it says: "Only uses ADC2 use pin P3". Hope to hear from the author of this driver (JonP) about possibility to include the second channel. Also It appears that another version of the Pmod driver was created by Analog Devices three years ago for use with the FPGAs. I did not try it and wonder if anyone can comment on it.
  9. I recently went to use my Analog Discovery 1 and I found that it was giving me all sorts of strange results that I did not expect. I figured that the calibration must have drifted since I hadn't used the device in a year or so, but when I performed a calibration it was still significantly off. Here's a link to an album showing comparisons between the AD1's readings versus a multimeter: . I don't really know what to do at this point, but perhaps someone here has run into this issue before and can recommend a fix. Thanks! Edit: For what it is worth, I have tried using different USB cables, different ports on my computer, different computers/operating systems, different jumper wires, and a different breadboard all to the same effect.
  10. Waveforms 2015 on Ubuntu 16.04.1 intermittently fails when selecting an AD1/AD2 device in Waveforms's Device Manager screen, reporting either or both of the following error messages. Subsequent attempts intermittently fail or intermittently succeed. --- Device opening failed --- JtscInitScanChain failed ERC: 0x3E9 Device programming failed. --- --- Device opening failed --- DptiIO failed ERC: 0x7 Device configuration failed (PLL 3). --- System configuration: digilent.adept.runtime_2.16.5-amd64.deb digilent.waveforms_3.4.7_amd64.deb Analog Discovery 1 Analog Discovery 2 $ uname -a Linux 4.4.0-31-generic #50-Ubuntu SMP Wed Jul 13 00:07:12 UTC 2016 x86_64 x86_64 x86_64 GNU/Linux $ cat /proc/cpuinfo processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 60 model name : Intel(R) Core(TM) i7-4910MQ CPU @ 2.90GHz stepping : 3 microcode : 0x1c cpu MHz : 2872.472 cache size : 8192 KB physical id : 0 siblings : 8 core id : 0 cpu cores : 4 apicid : 0 initial apicid : 0 fpu : yes fpu_exception : yes cpuid level : 13 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm epb tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid xsaveopt dtherm ida arat pln pts bugs : bogomips : 5786.61 clflush size : 64 cache_alignment : 64 address sizes : 39 bits physical, 48 bits virtual power management:
  11. PALM

    PMOD AD1 on Nexys4

    Hi, I recently purchased a nexys 4 board and a Pmod AD1 to get short latency audio input to the fpga. Is there any vhdl example available to get audio samples from the AD1? the Digilent ressource center does not have any ... thanks, Pierre
  12. Looks like the input diode D2 will clamp to cutin voltage of diode if input goes negative and the circuit will survive?