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Found 7 results

  1. We have purchased a ARTY A7 board, as well we are using VIVADO 2018.3 (IDE). We downloaded the board supported files from below link as under " (3.1) Installing Digilent Board Files". https://reference.digilentinc.com/vivado/installing-vivado/start In the downloaded files we get .prj file and XML format files , while using vivado 2018.3 tool, it accepts only .xpr, .ppr, .xise formats. Please suggest me how to use board supported files in vivado 2018.3.
  2. We have purchased a ARTY A7 board, as well we are using VIVADO 2018.3 (IDE). We downloaded the board supported files from below link as under " (3.1) Installing Digilent Board Files". https://reference.digilentinc.com/vivado/installing-vivado/start In the downloaded files we get .prj file and XML format files , while using vivado 2018.3 tool, it accepts only .xpr, .ppr, .xise formats. Please suggest me how to use board supported files in vivado 2018.3.
  3. We are suppose to add a library from here: https://github.com/Digilent/vivado-library/releases and add it to the projects IP repository list to be able to add the block in the IP Integrator. I have checked all the releases and i cant find the Pmod NIC100 anywhere, i think its called PmodNIC, but correct me if am wrong because i haven't seen it anywhere anyway. Until i find this IP, the Pmod is just another paperweight on my desk along with my stalled project, Please help. I am using the Arty A7: Artix-7 FPGA Development Board.
  4. All: I'd like to get your thoughts on the following question: In https://reference.digilentinc.com/_media/cmod_a7/cmod_a7_rm.pdf, page 9. The Analog input circuit describes using a voltage divider to step a 0 to 3.3 range to 0 to 1 as required by the analog inputs. What I am also noting (and have measured) is that the input has a 3.3K impedance. I've been trying to get a TMP36GZ temperature monitor to work with this input and now suspect based on this temperature sensor's spec that the 3.3K draws too much current for this high impedance device. Has anyone else had any experience with limitation on the these analog inputs due to their lower impedance? Peter
  5. Hi,Even though I think this board should be towards questions about Digilent boards specifically, see if you can help me (I tried Xilinx forums without success). I am using the XADC's Vaux4 and Vaux12 on my Cmod A7. However, I'm having difficulties implementing the simultaneous sampling function using the XADC Wizard (Vivado 2016.2). From the wizard I get the ADC module with one address_in "pin" and one data_out "pin". My question is, if it is sampling both pairs simultaneously, how do I access the data? Wouldn't it be necessary to have two data outputs, one for each pair? How does it work? Thank you guys for your time and patience,Leo
  6. Hello guys, this question is aimed primarily at Digilent staff but if anyone has an answer, I'm not choosy :-) I just got a CMOD A7 and I'm bringing it up by going through simple projects and tutorials. I'm stumped by this one : https://reference.digilentinc.com/learn/programmable-logic/tutorials/cmod-a7-getting-started-with-microblaze/start I've followed it to the letter, but reality diverges from the internet at step 13. There is nothing in my SDK's "Run As" menu. Why is that, and how can I fix this ? The whole tutorial never mentions the reset signal : how is it generated ? JTAG only ? Also, whenever I upload any bitstream to the FPGA, I get this message : WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. I've tried everything to appease Vivado but to no avail. I get this message even with this tutorial, yet it's never mentioned in any tutorial. Google wasn't any help. Could this be somehow related to my troubles in SDK ? I'm using Vivado 2016.1. Not to criticize, but a tutorial should "just work", otherwise there's not much point to it. Here I have several instructions I need to "interpret", for example, step 11 : "Make sure that the Cmod A7 is (...) connected to the host PC via both the JTAG USB port and the UART USB port." I see two COM ports when I plug the module in, but there's no way to tell which is which except trying to open one with Tera Term while Vivado's hardware manager is connected to the module (if it fails, that must be the JTAG). Also, while I understand that JTAG needs to be connected (and it seems to be, since I can program the device) why does to the UART need to be connected too ? And to what ? I tried having the UART connected to Tera Term while programming the FPGA from the SDK. Since the SDK mentions integrating the ELF into the bitstream, I expected at least to get the "Hello World" once the programming was complete, but got nothing. By the way, the module itself works : it runs the default code it ships with, and I do get the RAM test report coming out on the USB UART, so this isn't a hardware problem. I'm using Windows 10 but as far as I can tell this isn't an issue. I hope a good soul out there can spare a moment to help me :-) Edit : I'm going through the tutorial again with a fine-tooth comb. As early as project creation I get this warning : WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2016.1/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available Since I've selected the CMOD A7 A35T I don't get why Vivado would show this. I have checked the reset chain, it seems the board file sets button 0 as a reset source, active high, which matches the module's schematics. I don't know what I did differently but this time I got a full "Run As" menu at Step 13. However when I tried to launch the program I got a big error dialog box that told me : "Could not find FPGA device on the board for connection 'Local'." The board had been plugged in ever since I created the project in Vivado... I'll keep looking and update my question if I find anything new. Edit 2 : got a hunch that this last error could be due to some program not closing a COM port properly. So I re-launched the SDK, unplugged / replugged the module to force Windows to close its COM ports, re-programmed the FPGA with its bitstream... and then I tried Step 13 again. The "Run As" submenu was empty again for some reason (does anyone know ?) but "luckily" the System Debugger entry was still available in the Run Configurations dialog box. This time it worked, in that I got "Hello World" on the UART. Still, the whole process kinda smells of voodoo and instability at this point. Can we get clearer instructions in the tutorial ? Or are my problems due to some Windows 10 incompatibility or maybe using the wrong version of Vivado / SDK ?
  7. Leonardo

    Cmod A7 DIP Footprint

    Hi everyone, I want to use the Cmod A7-15T on a custom application and I would like to have the board's DIP footprint. Basically what I want to do is solder a female header to a PCB so I can stick the Cmod A7 into it. If you could provide me with the DIP dimensions that would be highly appreciated. Thanks, Leonardo