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Found 368 results

  1. Hi folks, I hope all is well with you. I am a newbie to zynq AP SoC. I started working with Digilent Zybo board, lwip ethernet echo server example. Problems facing. 1. Auto Negotiation failure if i set the link speed to auto in bsp. If i set link speed to 1000Mbps the program says that the ethernet link is down. 2. How to modify the echo server program where i can send and receive data to a specific ip address with specific port number as Server and also as client. I am using a Xilinx SDK version 2018.3 Operating system: Windows 10 Happy to hear a best possible solution from you folks. Thanks in advance. Regards Ajeeth kumar
  2. s224071

    VGA on Zybo

    Hello, First of all, I'm a beginner. I'd like to use my zybo board to print a simple image on a screen using the VGA port. I looked for some tutorials, but either they are all working on older version of Vivado (mine is 2016.4), therefore the vhdl file have compatibility problems, or they are not so clear about how to actually configure the board to use the VGA. I really just want to do something simple, like printing a static ball on the screen... Can somebody help me to understand how to do this? Gianluca
  3. Hello, I'm trying to make a standalone application for image processing on ZYBO, but I have problems with creating a block design which would make it possible. Since I started using Vivado two months ago, I'm still not familiar with creating my own block designs. I know that I should use dvi2rgb, Video In to AXI4-Stream and AXI VDMA IPs to store frames to DDR memory, but I don't know how to configure them. My idea is to create a function in Vivado SDK, e.g. CaptureImage(), which would return an address of the image saved in memory. Can somebody help me create the simplest block design to accomplish that? Best regards, Toni
  4. Hello, I would like to know if there is any way to build this project on Vivado 2018.3? Or the easiest way would be uninstalling this version and installing Vivado 2016.4 to build it? Cheers.
  5. Hi, I am trying to implement Audio Demo on Zybo Z7 using this: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-dma-audio-demo/start First, I wanted to do it just using Vivado 2018.2 (without SDK). I followed what is described in this comment: Bitstream is succesfully generated with two following warnings: [Labtools 27-3361] The debug hub core was not detected. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active. 2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'. For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908). I tried to fix this warnings using Xilinx and Diligent forum, but wasnt successful. Device is programmed but the audio demo is not working (when I press BTN1 and after BTN2 I can not hear anything on headphones). Any suggestions/solutions are very well welcomed. Regards,
  6. I'm trying to create a hardware using custom ip which capture button status in a register. But, error of multiple driver nets occurred. Could you help me to solve this error please ? I created project according to ZYBO tutorials as follows: 1. Create project and create new IP. 2. Edit IP: add port and logic in myip_v1_0_S00_AXI.v ------------------ // Users to add ports here input wire [3:0] MY_IN0, // User ports ends ------------------------ // Add user logic here always @( posedge S_AXI_ACLK ) begin if ( S_AXI_ARESETN == 1'b0 ) begin slv_reg1 <= 0; end else begin slv_reg1[3:0] <= MY_IN0; end end // User logic ends --------------- 3. Create Block Design: Add ZYNQ, my IP and external port and connect them. 4. Generate Block Design and Create HDL Wrapper 5. Open erabolated design: Connect myip ports to ZYBO button to generate xdc file. 6. Run synthesis is successfully completed. 7. Run implementation generate several errors. [DRC MDRV-1] Multiple Driver Nets: Net design_1_i/myip_0/inst/myip_v1_0_S00_AXI_inst/slv_reg1[0] has multiple drivers: design_1_i/myip_0/inst/myip_v1_0_S00_AXI_inst/slv_reg1_reg[0]/Q, and design_1_i/myip_0/inst/myip_v1_0_S00_AXI_inst/slv_reg1_reg[0]__0/Q. I attach the screen shot and my project. Anyone can help me, please ? project_6.zip
  7. Hi, I get infinite loops when I enter a digit which is not expected from scanf function while programming a standalone application for the retired version of zybo. what I want is to enter just an integer. I used the next code to avoid entering something that is not an integer by accident, as an alternative for scanf. This works great on CodeBlocks, but when I try to use it on SDK it does not work, it's like I cannot enter anything. How can I solve this issue? should I use another function or library? #include <stdio.h> #include <stdlib.h> int main(void) { char *p, s[100]; int n; while(1) { while (fgets(s, sizeof(s), stdin)) { n = strtol(s, &p, 10); if (p == s || *p != '\n') { printf("Please enter an integer: "); } else break; printf("You entered: %d\n", n); } printf("the number is %d\n",n); } }
  8. Hello, I am having trouble outputting sound on Linux using SSM2603. The SSM2603 device driver loads normally. It is also registered in ALSA sound card list. However, "input / output error" is raised in "alsactl init". ("amixer" is also the same.) It plays when I play wave file with "aplay" but it does not output to "R/LOUT pin" of SSM2603. Regards, Namio
  9. Hello, I'm currently am trying to configure the XADC_wizard IP to receive audio from the mic_in port of the board. I have opened the XADC demo that was provided and saw in the Verilog code that the ports for the PMOD were instantiated. Leading to the ZYBO_Master.xdc I saw both the ##I2S Audio Codec and ## Audio Codec/external EEPROM IIC bus. Would either of these help me in setting up the mic_in port? Objective: receive external audio from the mic_in port, run it through the ADC, and view the data received and if possible view it in a waveform. Thank you
  10. Hi! A couple of months ago, I bought a ZYBO Z7-10 board for one of my university labs. Just recently, I was using the JE PMOD ports to interface with an external LCD display. The board was programmed through QSPI Flash through the micro USB port. Unfortunately, a external 5 volt supply leaked into the 3v3 JE PMOD peripheral when the board was powered through the micro USB port. I immediately turned off the power supply and the ZYBO board once this had happened. After turning back on the ZYBO with all PMOD connections detached (to test if the board was still functional), the default demo program that the FPGA should run (with flashing all LEDs in a smooth manner) is a very erratic version of what it once was (LEDs flash randomly). While in the QSPI Flash mode (after the incident), I am not able to reprogram my FPGA design as Vivado does not recognize the ZYBO board anymore through the USB connection. When I change the programming mode jumper to either TJAG or MicroSD, Vivado CAN recognize the ZYBO board and I can successfully field-program the board and run the program. Is it possible that I have permanently damaged the QSPI Flash (or even something worse). If not, is there anything I could do to fix this?
  11. shurunxuan

    Zybo HDMI output help

    Hello everyone, I'm new to Zybo board and I have a question about it's HDMI port. Is Zybo's HDMI port capable of 3840x2160 video signal output at either 30fps or 60fps? If so, how should I modify the HDMI TX demo? I tried to add timing parameters for 3840x2160@30fps like this: static const VideoMode VMODE_3840x2160a30 = { .label = "3840x2160@30Hz", .width = 3840, .height = 2160, .hps = 4016, .hpe = 4104, .hmax = 4400, .hpol = 1, .vps = 2168, .vpe = 2178, .vmax = 2250, .vpol = 1, .freq = 297 }; But I always get 240MHz pixel clock frequency when the program runs, which results in "no signal" on my monitor. I guess this requires a change in the block diagram, but I need help on it. Thanks!
  12. Hi, I am working on Zybo and not entirely sure how the outputs will behave when 2 leds are connected as the figure shows. Pins JE1 and JE2 are configured as PWM outputs for the PL on the same port (JE single-ended standard Pmod port) and the VCC and GND pins shown in the figure are located on the same port as well. The usual thing to do is to supply energy to the external led as shown on the left of the figure, but can I connect a second led as shown on the right at the same time? I understand the if the pin is an output, then current should exit from it, but what happens when current enters? By the way.. I've tested both circuits independently (i'll wait an answer to connect both circuits at the same time) and they turn on the led with the respective duty cicle of each PWM, but still why does it work when a current enters the output pin?
  13. I am going through the Zynq Book Tutorial, version 1.3 April 2014. It seems the Zynqbook and Zynqbook Tutorial are leveled at Vivado 2014.x Zedboard and I have Vivado 2017.2 and Zybo Z4-20 board. Following example 1.B for the Zedboard, the tutorial states on page 15, "Click Run Connection Automation from the Designer Automation message at the top of the Diagram window and select /axi_gpio_0/GPIO." Then a dialog box labeled "Run Connection Automation" will appear. In my version of VIvado or Zybo constraints I don't get this popup window or a selection the looks like /axi_gpio_0/GPIO and now am at a loss on how to connect the AXI GPIO and LEDs. Is there a newer version of this book that includes the Zybo Z7-20 series? Thanks in advance.
  14. Hi there! Nice to meet you! Regards, Takeshi
  15. Gourav

    zybo hdmi to vga out

    Hello to all, i have start working on video processing through zybo board,so for that i have gone to digilent zybo video workshop file, its link is provided below http://web-pcm.cnfm.fr/wp-content/uploads/2017/04/Workbook-Digilent_ZYBO_Video_Workshop.pdf i gone through all steps carefully make all connection as shown in file but still nothing show Changes i have done in ip clocking wizard ip : sys_clock take 125mhz freq and set to mmcm at 200 mhz output dvi2rgb1v_7 ip : preferred resolution 1280*720 and other option as guided in file and other ip changes as provided in file Regarding error: their is no error or any critical warning is shown in vivado 2016.2 version bur still nothing shows,even though i have provided external power supply 5v to it and change jumper to its specific part edge detetion works fine and show rover output so i imported it in design and the complete design image i add in attachment.( i have twice check the hdmi cable ,vga projector and lp output all works fine) i have attach xdc file and desing image i m using zybo board having specific xc7z010clg400-1 part pls provide some solution or any other help ASAP Zybo_B.xdc
  16. mbo

    Zybo and PmodCAN

    Hello members, I have the Zybo-Z7 Board and I want to connect it with other Zybo-Z7 Board via CAN. The board has an integrated CAN Controller and I need following PmodCAN-Connector which has also can controller integrated. http://store.digilentinc.com/pmod-can-can-2-0b-controller-with-integrated-transceiver/ Which CAN Controller shall I use and how do I make it work? I have implemented a basic design for Zybo in Vivado and added the IP core for PmodCAN. Is something more I need? Cheers, mb
  17. @Bianca @Rainer Urian can you help me ? i am also working on zybo board and suffering from same problem. my usb port ( j10 and j9 ) are not getting detected . can you tell me how to resolve this issue ?
  18. Hi, I'm developing a design for the ZyBo and I'm using JTAG to communicate a PC with a microblaze. I'm using the onboard FT2232HQ to achieve this, but it is configured as UART -> Virtual COM Port and 245 FIFO -> D2XX Direct, so I can't see the JTAG connection as a COM port in the PC (which is what I need). I know that this can be changed using FT Prog, but I've seen that a lot of people had problems connecting the board with Vivado after changing the FT2232 configuration. Is it safe to make changes in the FT2232 configuration? Thanks, Xabier
  19. I know that RX / TX lines for UART connection are going to be swapped at one end or another. but why do you swap them for the status LED that are showing activity? When the Zybo board is sending a message the RX LED lights up?
  20. I see two COMs on device manager for my ZYBO SoC, this is a problem when I want to connect through SDK because it is supposed to have only one COM. Furthermore I have to say that this happens only on my new laptop which has vivado 2018 installed on it, when using my old laptop with vivado 2014 this is not a problem, I see just one COM, and the SDK software runs normally. I can program the bit file, but cannot connect using the SDK and even on laptops that do not have vivado installed, only one COM is shown. How can I fix this issue?
  21. hi Now i'm using ZYBO. I tried to send data from ZYBO to PC by ethernet communication. I already succeed to check lwip echo server example. (https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq-server/start). what i want to do is sending XADC data from PS to pc by ethernet. So, can i do this by modifying echo server code? Is there any example about this? or other method? thanks.
  22. When running from Xilinx SDK (2018.3) I cannot get the trivial "Hello world output" from my Zybo Z7 board. However I do get the following messages: Connected to /dev/ttyUSB1 at 115200 Initializing... init:done Zybo Z7-20 Rev. B Demo Image This means that I in general can talk to the port that appears in /dev most often as /dev/ttyUSB1 but at times under different number, so the problem is different from just being unable to get serial port working. The port was initially not accessible due permissions but I have worked around by changing them with chmod. I also added myself to dial group by s'udo adduser audrius dialout' . This has no effect. I have created the "Base Zynq" project with Vivado, generated bitstream without any changes to it, exported (Export hardware, include bitstream) and opened SDK using Vivado menu commands under "File" group. In SDK, I asked to create a new application project, standalone platform, "Hello world". I have selected "Program device" in SDK and passed this step without any obvious errors, with progress bar gradually moving as device is programmed. Also, Vivado shows the device temperature correctly. I noticed that when I do the device programming, the demo LEDs stop flashing in all colors. Only red LD13, green LD12 and green LD4 remain on. However when I attempt to run the project from SDK, multiple LEDs start flashing again, indicating that probably a reset has happened. At this point the "Zybo Z7-20 Rev B Demo Image" appears on the SDK terminal (115200 bauds) , so the terminal in general works. Looks like another "debug terminal" for two cores opens in SDK (TFC Debug Virtual Terminal cores 1 and 0) at this point but also remains empty. I have tried to change the stdout in BSP settings, but switching between "ps7_uart_1" and "ps7_coresight_com" results no changes in behavior. I tried to move the jumper JP5 between JTAG and QSP1. The "Demo image" message shows up in QSP1 position. In JTAG position, just nothing appears. I also tried to flash the bitstream from Vivado directly but this did not change anything. I have no problems in getting the output from KCU116 Microblaze after the similar sequence of actions but this is on another host (Window 7). I am using Ubuntu 16 (4.15.0-43-generic #46~16.04.1-Ubuntu SMP Fri Dec 7 13:31:08 UTC 2018 x86_64 x86_64 x86_64 GNU/Linux) I attach SDK logs and synthesis logs. Board files I have downloaded from https://github.com/Digilent/vivado-boards/archive/master.zip. After installing as described in https://reference.digilentinc.com/vivado/installing-vivado/start I was able to find and select the Zybo Z7 - 20 after restarting Vivado. While the board was initially powered by USB 3, I tried the 5 V wall adapter later, no changes. Last think I tried was connecting the pin aux_reset_in of the block rst_ps7_0_50M to constant value 1 in Vivado designer. It looks like reset signal with active low, so, thought, maybe not a good idea to left hanging as it is initially created. Yet was not helpful. Summarizing, looks like the demo image boots, and the card can be accessed and programmed by Xilinx tools, also serial port works, but the "Hello world" from SDK does not run at all or crashes immediately after start. sdk.log synthesis.log
  23. Hi, I have written a code in Verilog to control screen through VGA port and performed different transitions in color displaying on screen. But now I want to do the same thing from PS part of ZYBO. I don't know whether I have to use HDMI port for this purpose or something else. Please help me out from this problem and suggest me different tutorials to do this task if available Thanks in advance Regards,
  24. Hello, I am new to Zybo/FPGA and currently going thru the tutorial that's available. Currently at the DMA tutorial. From what I understand, there are 2 method to do the project, using SDK or Vivado. When I tried using SDK, I have a whole bunch of missing inlcudes like xparameters.h, xgpio.h, xstatus.h (to name a few). So, I went the Vivado route. When attempting to run the tcl script, I had errors on line 67. update_ip_catalog -rebuild. Was able to resolve that by using the vivado library. Now, I'm stuck with errors stating that IPs are locked. I am trying to follow this recommendation to change the version, but, I can't find the system.tcl file. Any suggestions?