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Found 377 results

  1. Hi, I'm working on ZYBO SoC. I want to boot it from QSPI flash but it fails anyhow. I have tried two methods using Vivado and IMPACT tool. 1. After successful implementation I created .bit and .bin files for a simple led_blinky project. Than I added "Configuration Memory Device" and selected Spansion s25fl128s 3.3v flash. I loaded the .bin file and then Erased, Verify and Programmed the flash step by step by checking the checkbox. The problem is with verify step. It fails every time. even then if I program it ignoring the failed verify step, it obliviously doesn't boots the program and no led blinks on board after resetting it. PS: I've taken care of the Jumpers already. 2. In the iMPACT tool I first created the PROM for a single FPGA, added 128MiB and created a .mcs file from the .bit file. then I initialized chain and after successful detection of board I added SPI Flash (which is attached above the ARM in the workspace figure) and loaded the flash with .mcs file. than I get option to either Erase, Verify or Program the flash. here too the program fails at Verify Step. Please help out.
  2. I want to use GNU RADIO to design an RF signal receiving circuit. For this I plan to use an FPGA card in the baseband section of the circuit (to handle the decimation and, if possible, to convert analogue to digital signal). My doubt lies in knowing if it is possible to communicate the FPGA card to the GNU RADIO application directly or if necessary from an external program. At this point it should be noted that I work in windows 10. I'm quite new on the subject of FPGA and GNU RADIO. I would really be grateful if you help me with this problem. The card is a Xilinx Zynq-7000 Developmet Board, the Z-7010, its features are best seen on the next page Suggestions for design changes are welcome. In advance thanks for the help.
  3. Any & all help is appreciated with this thread. I am 100% new rookie to FPGA. I purchased the Digilent Zybo Z7: Zynq-7000 ARM/FPGA SoC Development Board (Zybo Z7-20 with SDSoC Voucher) My intentions are to crypto currency mine a new FPGA algo called Odocrypt created by the blockchain group Digibyte DGB. Here are a couple links to the info. DigiByteCoin Github Odocrypt Mining Software It will change every 10 days. Its supposed to, to make it more ASIC resistant. I thought this may make a nice marketing tool also that is profitable & I'll gladly promote if someone can tell me how to set it up! Any input, insight or suggestions how to setup the Xilinx software for this particular FPGA to mine that Odocrypt algo on that mining pool... would be greatly appreciated! TYIA
  4. When running from Xilinx SDK (2018.3) I cannot get the trivial "Hello world output" from my Zybo Z7 board. However I do get the following messages: Connected to /dev/ttyUSB1 at 115200 Initializing... init:done Zybo Z7-20 Rev. B Demo Image This means that I in general can talk to the port that appears in /dev most often as /dev/ttyUSB1 but at times under different number, so the problem is different from just being unable to get serial port working. The port was initially not accessible due permissions but I have worked around by changing them with chmod. I also added myself to dial group by s'udo adduser audrius dialout' . This has no effect. I have created the "Base Zynq" project with Vivado, generated bitstream without any changes to it, exported (Export hardware, include bitstream) and opened SDK using Vivado menu commands under "File" group. In SDK, I asked to create a new application project, standalone platform, "Hello world". I have selected "Program device" in SDK and passed this step without any obvious errors, with progress bar gradually moving as device is programmed. Also, Vivado shows the device temperature correctly. I noticed that when I do the device programming, the demo LEDs stop flashing in all colors. Only red LD13, green LD12 and green LD4 remain on. However when I attempt to run the project from SDK, multiple LEDs start flashing again, indicating that probably a reset has happened. At this point the "Zybo Z7-20 Rev B Demo Image" appears on the SDK terminal (115200 bauds) , so the terminal in general works. Looks like another "debug terminal" for two cores opens in SDK (TFC Debug Virtual Terminal cores 1 and 0) at this point but also remains empty. I have tried to change the stdout in BSP settings, but switching between "ps7_uart_1" and "ps7_coresight_com" results no changes in behavior. I tried to move the jumper JP5 between JTAG and QSP1. The "Demo image" message shows up in QSP1 position. In JTAG position, just nothing appears. I also tried to flash the bitstream from Vivado directly but this did not change anything. I have no problems in getting the output from KCU116 Microblaze after the similar sequence of actions but this is on another host (Window 7). I am using Ubuntu 16 (4.15.0-43-generic #46~16.04.1-Ubuntu SMP Fri Dec 7 13:31:08 UTC 2018 x86_64 x86_64 x86_64 GNU/Linux) I attach SDK logs and synthesis logs. Board files I have downloaded from After installing as described in I was able to find and select the Zybo Z7 - 20 after restarting Vivado. While the board was initially powered by USB 3, I tried the 5 V wall adapter later, no changes. Last think I tried was connecting the pin aux_reset_in of the block rst_ps7_0_50M to constant value 1 in Vivado designer. It looks like reset signal with active low, so, thought, maybe not a good idea to left hanging as it is initially created. Yet was not helpful. Summarizing, looks like the demo image boots, and the card can be accessed and programmed by Xilinx tools, also serial port works, but the "Hello world" from SDK does not run at all or crashes immediately after start. sdk.log synthesis.log
  5. Hi, I am trying to interface XADC on Zybo with xillyubus to measure external analog values.Rest of the design is working okay with a counter.My Question is how do i connect XADC with the xillybus Ip Core. any help is appreciated thank you
  6. Hello, I try to generate a VGA signal with a VDMA, Video Timing, and AXI4 Stream to Video Out IP for my Zybo. So I create the following block design with the given settings (Note: I test the design with the test pattern generator instead of the VDMA before, so I know that the settings of the Timing Generator and Video Out IP are correct). My code looks like this: #ifdef WITH_TESTPATTERN #include "xv_tpg.h" #endif #include "xaxivdma.h" #include "xparameters.h" #ifdef WITH_TESTPATTERN XV_tpg TPG; XV_tpg_Config* TPG_Config; #endif XAxiVdma_Config* VDMA_Config; XAxiVdma VDMA; XAxiVdma_DmaSetup ReadConfiguration; unsigned int frame_buffer[800][600][3]; unsigned int srcBuffer; u32 Status; void fill(void) { for(u32 i = 0x00; i < 800; i++) { for(u32 j = 0x00; j < 600; j++) { frame_buffer[i][j][0] = 0xFF; frame_buffer[i][j][1] = 0xFF; frame_buffer[i][j][2] = 0xFF; } } } int main() { #ifdef WITH_TESTPATTERN TPG_Config = XV_tpg_LookupConfig(XPAR_TESTPATTERN_DEVICE_ID); if(!TPG_Config) { xil_printf("Error during test pattern generator configuration!\n\r"); return -1; } Status = XV_tpg_CfgInitialize(&TPG, TPG_Config, TPG_Config->BaseAddress); if(Status != XST_SUCCESS) { xil_printf("Error during test pattern generator initialization!\n\r"); return -1; } XV_tpg_Set_height(&TPG, 600); XV_tpg_Set_width(&TPG, 800); XV_tpg_Set_bckgndId(&TPG, 0x0C); XV_tpg_EnableAutoRestart(&TPG); XV_tpg_Start(&TPG); #endif VDMA_Config = XAxiVdma_LookupConfig(XPAR_VIDEODMA_DEVICE_ID); if(!VDMA_Config) { xil_printf("Error during VDMA configuration!\n\r"); return -1; } Status = XAxiVdma_CfgInitialize(&VDMA, VDMA_Config, VDMA_Config->BaseAddress); if(Status != XST_SUCCESS) { xil_printf("Error during VDMA initialization!\n\r"); return -1; } ReadConfiguration.VertSizeInput = 600; ReadConfiguration.HoriSizeInput = 800 * (VDMA_Config->Mm2SStreamWidth >> 3); ReadConfiguration.Stride = 800 * (VDMA_Config->Mm2SStreamWidth >> 3); ReadConfiguration.FrameDelay = 0; ReadConfiguration.EnableCircularBuf = 1; ReadConfiguration.EnableSync = 0; ReadConfiguration.PointNum = 0; ReadConfiguration.EnableFrameCounter = 0; ReadConfiguration.FixedFrameStoreAddr = 0; Status = XAxiVdma_DmaConfig(&VDMA, XAXIVDMA_READ, &ReadConfiguration); if(Status != XST_SUCCESS) { xil_printf("Read channel configuration failed!\n\r"); return -1; } fill(); Status = XAxiVdma_DmaSetBufferAddr(&VDMA, XAXIVDMA_READ, (UINTPTR*)frame_buffer); if(Status != XST_SUCCESS) { xil_printf("Read channel set buffer address failed!\n\r"); return -1; } Status = XAxiVdma_DmaStart(&VDMA, XAXIVDMA_READ); if(Status != XST_SUCCESS) { xil_printf("Failed to start DMA engine (read channel)!\n\r"); return -1; } xil_printf("Start...\n\r"); while(1) { } return 0; } But the monitor doesn´t show the picture (and no message that the signal is missing, so HSync and VSync work) and I´ve got the terminal message Read channel set buffer address failed! So what is wrong with the code? Thank you guys
  7. Hello, I am a college student currently working on the HDMI Input demo for the Zybo board on Vivado 2018.3 and SDK. I am following the steps provided on this forum, but I end up with trouble displaying the HDMI source onto the monitor. Without any modification, I can get the HDMI source to display properly; however, there seems to be many errors and warnings. In addition, modifying the C code by commenting out some of the switch statements resulted in no change whatsoever. After creating a new bsp and application project, followed by copy and pasting all of the source files, I had no errors popping up. I was able to see the results of the modifications I made, but the HDMI source wouldn't display onto the monitor (just the DemoPrintTest shows up). I have posted my project onto this link. If possible, I would like to get help on this matter.
  8. Hi Is it possible to implement DVFS technique on FPGA board (i have zybo zynq-7000).
  9. Brain

    zybo zynq-7000 SD boot

    Hello, I followed a few tutorials online and was able to boot a hello world project from an SD card. Is possible to Boot a project without going to SDK, my project is mainly hardware so it is only in the PL side of the board. I tried to do it with the XADC demo but I couldn't figure it out.
  10. hello, I am new to designing with pmod wifi. I want to send audio files from pc to the zybo via pmod wifi and then process it then play it via output port. is it as easy as that example showed here? Bests, Meysam Sh.
  11. Hello, I'm currently am trying to configure the XADC_wizard IP to receive audio from the mic_in port of the board. I have opened the XADC demo that was provided and saw in the Verilog code that the ports for the PMOD were instantiated. Leading to the ZYBO_Master.xdc I saw both the ##I2S Audio Codec and ## Audio Codec/external EEPROM IIC bus. Would either of these help me in setting up the mic_in port? Objective: receive external audio from the mic_in port, run it through the ADC, and view the data received and if possible view it in a waveform. Thank you
  12. Mukul

    Data compression

    I'm working on Data compression so studying different code techniques such as follows to implement on zybo board Golomb coding special case Rice code compression Huffman code Arithmetic code And finally Dynamic Markov compression I selected DMC because it is dynamic in nature and work well with sensor (as input).Here is the problem that i don't know exactly markov compression is good for this or not. Also when i study the DMC it's algorithm is similar to sequence detector (so are they same?). Secondly in video processing/image processing or in general which tech. Is used in Data compression.
  13. Hi folks, I hope all is well with you. I am a newbie to zynq AP SoC. I started working with Digilent Zybo board, lwip ethernet echo server example. Problems facing. 1. Auto Negotiation failure if i set the link speed to auto in bsp. If i set link speed to 1000Mbps the program says that the ethernet link is down. 2. How to modify the echo server program where i can send and receive data to a specific ip address with specific port number as Server and also as client. I am using a Xilinx SDK version 2018.3 Operating system: Windows 10 Happy to hear a best possible solution from you folks. Thanks in advance. Regards Ajeeth kumar
  14. s224071

    VGA on Zybo

    Hello, First of all, I'm a beginner. I'd like to use my zybo board to print a simple image on a screen using the VGA port. I looked for some tutorials, but either they are all working on older version of Vivado (mine is 2016.4), therefore the vhdl file have compatibility problems, or they are not so clear about how to actually configure the board to use the VGA. I really just want to do something simple, like printing a static ball on the screen... Can somebody help me to understand how to do this? Gianluca
  15. Hello, I'm trying to make a standalone application for image processing on ZYBO, but I have problems with creating a block design which would make it possible. Since I started using Vivado two months ago, I'm still not familiar with creating my own block designs. I know that I should use dvi2rgb, Video In to AXI4-Stream and AXI VDMA IPs to store frames to DDR memory, but I don't know how to configure them. My idea is to create a function in Vivado SDK, e.g. CaptureImage(), which would return an address of the image saved in memory. Can somebody help me create the simplest block design to accomplish that? Best regards, Toni
  16. Hello, I would like to know if there is any way to build this project on Vivado 2018.3? Or the easiest way would be uninstalling this version and installing Vivado 2016.4 to build it? Cheers.
  17. Hi, I am trying to implement Audio Demo on Zybo Z7 using this: First, I wanted to do it just using Vivado 2018.2 (without SDK). I followed what is described in this comment: Bitstream is succesfully generated with two following warnings: [Labtools 27-3361] The debug hub core was not detected. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active. 2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'. For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908). I tried to fix this warnings using Xilinx and Diligent forum, but wasnt successful. Device is programmed but the audio demo is not working (when I press BTN1 and after BTN2 I can not hear anything on headphones). Any suggestions/solutions are very well welcomed. Regards,
  18. I'm trying to create a hardware using custom ip which capture button status in a register. But, error of multiple driver nets occurred. Could you help me to solve this error please ? I created project according to ZYBO tutorials as follows: 1. Create project and create new IP. 2. Edit IP: add port and logic in myip_v1_0_S00_AXI.v ------------------ // Users to add ports here input wire [3:0] MY_IN0, // User ports ends ------------------------ // Add user logic here always @( posedge S_AXI_ACLK ) begin if ( S_AXI_ARESETN == 1'b0 ) begin slv_reg1 <= 0; end else begin slv_reg1[3:0] <= MY_IN0; end end // User logic ends --------------- 3. Create Block Design: Add ZYNQ, my IP and external port and connect them. 4. Generate Block Design and Create HDL Wrapper 5. Open erabolated design: Connect myip ports to ZYBO button to generate xdc file. 6. Run synthesis is successfully completed. 7. Run implementation generate several errors. [DRC MDRV-1] Multiple Driver Nets: Net design_1_i/myip_0/inst/myip_v1_0_S00_AXI_inst/slv_reg1[0] has multiple drivers: design_1_i/myip_0/inst/myip_v1_0_S00_AXI_inst/slv_reg1_reg[0]/Q, and design_1_i/myip_0/inst/myip_v1_0_S00_AXI_inst/slv_reg1_reg[0]__0/Q. I attach the screen shot and my project. Anyone can help me, please ?
  19. Hi, I get infinite loops when I enter a digit which is not expected from scanf function while programming a standalone application for the retired version of zybo. what I want is to enter just an integer. I used the next code to avoid entering something that is not an integer by accident, as an alternative for scanf. This works great on CodeBlocks, but when I try to use it on SDK it does not work, it's like I cannot enter anything. How can I solve this issue? should I use another function or library? #include <stdio.h> #include <stdlib.h> int main(void) { char *p, s[100]; int n; while(1) { while (fgets(s, sizeof(s), stdin)) { n = strtol(s, &p, 10); if (p == s || *p != '\n') { printf("Please enter an integer: "); } else break; printf("You entered: %d\n", n); } printf("the number is %d\n",n); } }
  20. Hello, I am having trouble outputting sound on Linux using SSM2603. The SSM2603 device driver loads normally. It is also registered in ALSA sound card list. However, "input / output error" is raised in "alsactl init". ("amixer" is also the same.) It plays when I play wave file with "aplay" but it does not output to "R/LOUT pin" of SSM2603. Regards, Namio
  21. Hi! A couple of months ago, I bought a ZYBO Z7-10 board for one of my university labs. Just recently, I was using the JE PMOD ports to interface with an external LCD display. The board was programmed through QSPI Flash through the micro USB port. Unfortunately, a external 5 volt supply leaked into the 3v3 JE PMOD peripheral when the board was powered through the micro USB port. I immediately turned off the power supply and the ZYBO board once this had happened. After turning back on the ZYBO with all PMOD connections detached (to test if the board was still functional), the default demo program that the FPGA should run (with flashing all LEDs in a smooth manner) is a very erratic version of what it once was (LEDs flash randomly). While in the QSPI Flash mode (after the incident), I am not able to reprogram my FPGA design as Vivado does not recognize the ZYBO board anymore through the USB connection. When I change the programming mode jumper to either TJAG or MicroSD, Vivado CAN recognize the ZYBO board and I can successfully field-program the board and run the program. Is it possible that I have permanently damaged the QSPI Flash (or even something worse). If not, is there anything I could do to fix this?
  22. shurunxuan

    Zybo HDMI output help

    Hello everyone, I'm new to Zybo board and I have a question about it's HDMI port. Is Zybo's HDMI port capable of 3840x2160 video signal output at either 30fps or 60fps? If so, how should I modify the HDMI TX demo? I tried to add timing parameters for 3840x2160@30fps like this: static const VideoMode VMODE_3840x2160a30 = { .label = "3840x2160@30Hz", .width = 3840, .height = 2160, .hps = 4016, .hpe = 4104, .hmax = 4400, .hpol = 1, .vps = 2168, .vpe = 2178, .vmax = 2250, .vpol = 1, .freq = 297 }; But I always get 240MHz pixel clock frequency when the program runs, which results in "no signal" on my monitor. I guess this requires a change in the block diagram, but I need help on it. Thanks!
  23. Hi, I am working on Zybo and not entirely sure how the outputs will behave when 2 leds are connected as the figure shows. Pins JE1 and JE2 are configured as PWM outputs for the PL on the same port (JE single-ended standard Pmod port) and the VCC and GND pins shown in the figure are located on the same port as well. The usual thing to do is to supply energy to the external led as shown on the left of the figure, but can I connect a second led as shown on the right at the same time? I understand the if the pin is an output, then current should exit from it, but what happens when current enters? By the way.. I've tested both circuits independently (i'll wait an answer to connect both circuits at the same time) and they turn on the led with the respective duty cicle of each PWM, but still why does it work when a current enters the output pin?
  24. I am going through the Zynq Book Tutorial, version 1.3 April 2014. It seems the Zynqbook and Zynqbook Tutorial are leveled at Vivado 2014.x Zedboard and I have Vivado 2017.2 and Zybo Z4-20 board. Following example 1.B for the Zedboard, the tutorial states on page 15, "Click Run Connection Automation from the Designer Automation message at the top of the Diagram window and select /axi_gpio_0/GPIO." Then a dialog box labeled "Run Connection Automation" will appear. In my version of VIvado or Zybo constraints I don't get this popup window or a selection the looks like /axi_gpio_0/GPIO and now am at a loss on how to connect the AXI GPIO and LEDs. Is there a newer version of this book that includes the Zybo Z7-20 series? Thanks in advance.
  25. Hi there! Nice to meet you! Regards, Takeshi