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Found 216 results

  1. Hi Everyone, Just accidentally flashed the EEPROM attached to the FT2232 device on the Arty. The board is dead without the USB connection. Been using for 2 months without issues until today. In Vivado it is showing: "ERROR: [Labtoolstcl 44-469] There is no current hw_target.". when trying to Auto Connect with the target in Hardware Manager. Within FT_Prog (FTDI's flash tool), the registers (e.g. serial number, vendor ID, D2XX/VCP driver ...) can all be read and modified. How can it be restored back to Digilent factory setting? Is there an FT_Prog template that we can use? Thanks, Robin
  2. Is there a way to stop generating the temporary files in below directory while accessing hw_server using Digilent cable. We are using Vivado 2018.3 to access the HW. Ø /tmp/digilent-adept2- Ø /dev/shm/diligent-adept2-* For some reason, few of these files appear to become “stuck” in the locked position on occasion which is what causes the below error: TCF 14:00:21.002: jtagpoll: cannot get port description list: ftdidb_lock failed: FTDMGR wasn't properly initialized TCF 14:00:21.012: jtagpoll: cannot get port description list: JTAG device enumeration failed: Initialization of the DPCOMM library failed. …above Errors are generate when hw_server was ran before Quick Search suggested a driver issue but if I delete the tmp files then it works fine. Any suggestions would be appreciated! Thanks HJ
  3. Hi - I just tried to install the XUP USB-JTAG Programming Cable from diligent. I also have a Diligent Programming Cable. Centos can see both cables (see below) Vivado can see the Diligent programming cable but not the Xilinx one. Given the physical constraints of the installation only the Xilinx one will work. Are there any specific instructions to get the Xilinx cable going? $lsusb | grep "Xilinx/|Future" Bus 002 Device 003: ID 03fd:000d Xilinx, Inc. Bus 001 Device 006: ID 0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC
  4. Sduru

    AXI4 and Vivado ILA

    Hello, My question is related to AXI4 usage in digital image processing. As I am new in image processing with HDL coding, I need to get this valuable answer from you @jpeyron @zygot @JColvin especially. I am using Zybo Z7 and PCAM 5C for my project. As a good start in my opinion, I wanna get digital image from CMOS through D-PHY and MIPI CSI-2 RX. And then, I just wanna scope the digital image bits by using Integrated Logic Analyzer (ILA). For this purpose, do I have to use AXI4 streaming and/or other AXI IPs in my VHDL design? In other words, can I pass the data from CSI-2 interface to ILA directly? If it is possible only with AXI interface, so I will deeply study the AXI4 referance manuals. Many thanks...
  5. Hello, I am a college student currently working on the HDMI Input demo for the Zybo board on Vivado 2018.3 and SDK. I am following the steps provided on this forum, but I end up with trouble displaying the HDMI source onto the monitor. Without any modification, I can get the HDMI source to display properly; however, there seems to be many errors and warnings. In addition, modifying the C code by commenting out some of the switch statements resulted in no change whatsoever. After creating a new bsp and application project, followed by copy and pasting all of the source files, I had no errors popping up. I was able to see the results of the modifications I made, but the HDMI source wouldn't display onto the monitor (just the DemoPrintTest shows up). I have posted my project onto this link. https://drive.google.com/open?id=1lvM1tz8zgd_w3UtlYuTKOEKojWYyn3rg If possible, I would like to get help on this matter.
  6. Sduru

    MIPI D-PHY and CSI-2

    Hi everyone, I am dealing with MIPI CSI-2 RX and D-PHY RX IPs which are open source IPs by Digilent. Where is the latest versions of those IPs? Is there new versions of those which are compatible with Vivado 2018.3? Many thanks...
  7. I followed the directions to a forum that show how to install board files into Vivado. Link: My issue comes when I close Vivado and reopen to create a new project, I don't see an option for selecting a nexys4 ddr board, like if I were looking for a Zybo board. I believe I copied the files over correctly. When selecting a board in Vivado, is it under a different name or would it say "nexy4 ddr"?
  8. Hi, I have a brand new Digilent A7-35T board I tried to program via the USB built in JTAG using Vivado 2018.2. The part intermittently shows up in Hardware Manager, but a seconds later disconnects. Sometimes it disconnects just being connected (opened) in Hardware Manager and sometimes during programming. It is even worse if I try to erase and program the QSPI flash. I also downloaded and installed the latest Digilent Adept 2 with updated drivers and observed the same behavior. I tried different USB cables, different USB ports directly on my PC, via a powered hub, but the behavior is always the same -- it intermittently disconnects and fails. The amber LED does however stay lit. In Device Manager I am able to see the FTDI UART. I did also see it enumerate as a Microsoft BallPoint Mouse -- whatever that is. With this exact same setup, PC, Vivado, USB cables, etc, I have been programming the Zybo Z7-20 and the Arty boards with several designs without any such issues. Please let me know if I missed anything and what are the next steps in getting the board replaced or fixed. Thanks.
  9. Hi All: I'm fairly new to both Verilog and the Basys3 board. I'm working thru a 'self education' course. I'm having a problem with the following module. I could use any answers/advice I can get. The module, as posted (below) is processed by Vivado properly, loads into the Basys3 board and runs as expected with the LED blinking at a frequency of .7451 Hz. No problems. The example I'm working thru then threw out a 'challenge' of changing the frequency of the blinking LED based on the positions of two switches [1:0]. 1. I added in the additional input - input [1:0] sw 2. I added in the case statement (which is currently commented out) 3. I commented out the original assignment of led - //assign led = clkdiv[26]; The problem crops up immediately with a Verilog error showing on the following line: case(sw) - The error states: Error: 'sw' is not a constant I've spent hours trying various changes...all to no avail. HELP....PLEASE!!!! Thanks Tons! VERILOG MODULE: module clk_divider( input clk, input rst, input [1:0] sw, output led ); wire [26:0] din; wire [26:0] clkdiv; dff dff_inst ( .clk(clk), .rst(rst), .D(din[0]), .Q(clkdiv[0]) ); genvar i; generate for (i = 1; i < 27; i=i+1) begin : dff_gen_label dff dff_inst ( .clk(clkdiv[i-1]), .rst(rst), .D(din), .Q(clkdiv) ); end endgenerate assign din = ~clkdiv; /* begin case(sw) 2'b00: assign led = clkdiv[26]; 2'b01: assign led = clkdiv[25]; 2'b10: assign led = clkdiv[24]; 2'b11: assign led = clkdiv[23]; default: assign led = clkdiv[26]; endcase end */ assign led = clkdiv[26]; endmodule
  10. s224071

    VGA on Zybo

    Hello, First of all, I'm a beginner. I'd like to use my zybo board to print a simple image on a screen using the VGA port. I looked for some tutorials, but either they are all working on older version of Vivado (mine is 2016.4), therefore the vhdl file have compatibility problems, or they are not so clear about how to actually configure the board to use the VGA. I really just want to do something simple, like printing a static ball on the screen... Can somebody help me to understand how to do this? Gianluca
  11. Hello, I would like to know if there is any way to build this project on Vivado 2018.3? Or the easiest way would be uninstalling this version and installing Vivado 2016.4 to build it? Cheers.
  12. Hello Digilent Community, I am working on a image processing project and was wondering if anyone had advice or could point me in the right direction. I have tried following some tutorials and example projects, but I am still trying to wrap my head around Xilinx Vivado and SDK. The project really shouldn't be very difficult, I think I am just missing some information or the best way to go about doing it. For the project I am using the Zybo z7-20 development board and want to save two images to an SD card. The two pictures are black and white frames from a video just seconds apart, so there is only slight change in the frames themselves. I want to compare the two frames and output either a black and white image of the change in pixels or a binary file of '0' being an unchanged pixel and '1' being a change in the pixel. MATLAB has the 'Computer Vision System Toolbox' 'Tracking Cars Using Foreground Detection' Simulink example that is similar to what I want to do on the Zybo z7-20 FPGA. The following figure show the original video (right) with blob detection (the green square) and the binary output image of the change in pixels in the foreground (left). I want to use the Zynq Processor and write C code to do the analysis, but I haven't found a clear way to access the SD card from the Xilinx SDK. The following figure is of my current Block Design with only the Zynq Processor as well as some GPIO to test. I am still researching and looking at examples to compare, but wanted to see if the community had any pointers or if someone has done this before. I am a college student and I have been really interested FPGA's and digital design for the past 6-9 months, but I have mainly written my own Verilog code and haven't worked with block design or running C code on any of my designs. Any comments or suggestions would be great. Thanks!
  13. I am following the steps outlined in https://reference.digilentinc.com/vivado/getting-started-with-ipi/start I am using a zybo-Z7-20 board and specifying VHDL. I have successfully completed the design and can modify the 'C' code in the xilinx SDK using the zynq processor. I am having trouble attempting to complete the same feat using a MicroBlaze processor. The fatal problem occurs in step 5.3 when generating the Bitstream. In various attempts the errors center around 2 unassigned ports. Here is the latest. [DRC NSTD-1] Unspecified I/O Standard: 2 out of 11 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. [DRC UCIO-1] Unconstrained Logical Port: 2 out of 11 logical ports have no user assigned specific location constraint (LOC). I have attached the full error and block design. ---- I wish to add a couple of comments regarding Vivado. In my installation on two different computers; in step 5.2 when defining the Top Module, the 5.2 recipe does not work for me on these two Windows installations. However, if one exits Vivado and restarts Vivado, the top module magically appears. However, if one starts Vivado from its desktop icon, Vivado get confused as to what is its project name. If one starts Vivado at this point from the file name in the project directory (ProjectName.xpr) the problem goes away. (See attachment VivadoProjName.JPG, project name is GettingStarted_3) GettingStarted_error.txt
  14. Could I get voucher license having ARTY A7 board without one in the kit? I bought the new ARTY A7 but it doesn't have voucher license in the box. Thanks in advance)
  15. I plan on purchasing the Zybo z7-20 for prototyping a project I am working on. After looking at the documentation for the board it says that Vivado WebPack supports the Zybo z7 board and is fully compatible with Design Suite. I just want to make sure that Xilinx Vivado WebPack works with this board. Thanks
  16. Please confirm if the Basys 3 Artix-7 FPGA Trainer Board is supported by the Vivado System Generator on Simulink®.
  17. When I try to program my board after I generated the .bit/.bin files, i get the following error [Labtoolstcl 44-26] No hardware targets exist on the server [TCP:localhost:3121]Check to make sure the cable targets connected to this machine are properly connectedand powered up, then use the disconnect_hw_server and connect_hw_server commandsto re-register the hardware targets.it says no hardware exists on the server, even though my board is plugged in with the mode jumper in the JTAG position. I also tried reinstalling Vivado to make sure the cable drivers were installed.
  18. Hi, I'm developing a design for the ZyBo and I'm using JTAG to communicate a PC with a microblaze. I'm using the onboard FT2232HQ to achieve this, but it is configured as UART -> Virtual COM Port and 245 FIFO -> D2XX Direct, so I can't see the JTAG connection as a COM port in the PC (which is what I need). I know that this can be changed using FT Prog, but I've seen that a lot of people had problems connecting the board with Vivado after changing the FT2232 configuration. Is it safe to make changes in the FT2232 configuration? Thanks, Xabier
  19. Hi All, I am beginner in FPGA world. I am trying to learn how to work with Vivado IP Integrator. When i try to launch my firstProj on Launch on Hardware(System Debugger) I am getting a such kind of issue: make all Building file: ../main.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"main.o" -I../../firstproj_bsp/microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"main.d" -MT"main.o" -o "main.o" "../main.c" Finished building: ../main.c Building target: firstproj.elf Invoking: MicroBlaze gcc linker mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../firstproj_bsp/microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "firstproj.elf" ./main.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group /opt/Xilinx/SDK/2018.2/gnu/microblaze/lin/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld: firstproj.elf section `.heap' will not fit in region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' makefile:35: recipe for target 'firstproj.elf' failed /opt/Xilinx/SDK/2018.2/gnu/microblaze/lin/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld: region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' overflowed by 1168 bytes collect2: error: ld returned 1 exit status make: *** [firstproj.elf] Error 1 19:49:21 Build Finished (took 335ms) I try to search on google but cannot to find an answer. Can someone help to understand the reason? I am thiinking that this may be some tool setup issue. Thanks!
  20. I seem to be having a similar issue with my Arty Z7 as this poster. At one point, my board was booting just fine from flash (via QSPI) or an SD card (with FSB, bistream, and SDK program). However, something happened along the way and I have to press the PROG button every time I power it up to boot it (true for either QSPI flash or SD). Only after I do this does the DONE light light up and the SDK program runs. My bitstream isn't compressed and I'm using Vivado 2018.2. I haven't messed with any of the bitstream or device properties. Any ideas? Thanks!
  21. I am a senior electrical engineering student and I just had my first interview at a local technology company and they offered me a second interview! However, they gave me a problem to solve of which i am pretty far into to it, at least far enough to start simulating some components. I am new to vivado and FPGA's in general and I have spent about 5 hours today trying to figure this error out. My code shows zero warnings or errors and I verified that the file in question is indeed in the directory that it is looking for. Wondering if anyone else has run into anything similar? Log Stuff: Tcl Console output when trying to simulate: launch_simulation INFO: [Vivado 12-5682] Launching behavioral simulation in 'F:/VHDL_Projects/Xilinx_Projects/Vivado_F5_CoffeeMaker/Vivado_F5_CoffeeMaker.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-54] Inspecting design source files for 'Entry_MachineTB' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'F:/VHDL_Projects/Xilinx_Projects/Vivado_F5_CoffeeMaker/Vivado_F5_CoffeeMaker.sim/sim_1/behav/xsim' "xvhdl --incr --relax -prj Entry_MachineTB_vhdl.prj" The system cannot find the file specified. INFO: [USF-XSim-69] 'compile' step finished in '1' seconds ERROR: [USF-XSim-62] 'compile' step failed with error(s) while executing 'F:/VHDL_Projects/Xilinx_Projects/Vivado_F5_CoffeeMaker/Vivado_F5_CoffeeMaker.sim/sim_1/behav/xsim/compile.bat' script. Please check that the file has the correct 'read/write/execute' permissions and the Tcl console output for any other possible errors or warnings. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. Batch File: 'F:/VHDL_Projects/Xilinx_Projects/Vivado_F5_CoffeeMaker/Vivado_F5_CoffeeMaker.sim/sim_1/behav/xsim/compile.bat' script is: @echo off REM **************************************************************************** REM Vivado (TM) v2018.3 (64-bit) REM REM Filename : compile.bat REM Simulator : Xilinx Vivado Simulator REM Description : Script for compiling the simulation design source files REM REM Generated by Vivado on Sat Jan 19 23:30:54 -0800 2019 REM SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 REM REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. REM REM usage: compile.bat REM REM **************************************************************************** echo "xvhdl --incr --relax -prj Entry_MachineTB_vhdl.prj" call xvhdl --incr --relax -prj Entry_MachineTB_vhdl.prj -log xvhdl.log call type xvhdl.log > compile.log if "%errorlevel%"=="1" goto END if "%errorlevel%"=="0" goto SUCCESS :END exit 1 :SUCCESS exit 0 I have verified that the "Entry_MachineTB_vhdl.prj" file is indeed in the same directory as the batch file. if needed, i can provide the code that i am working on. Thanks for any help provided!! :D
  22. Hi All, Is there anybody have any experience about XUP (Xilinx University Program) USB-JTAG Programmer Revision-G using with Vivado 2015 or 2018? I have some little experience with Vivado 2015.5 and 2018.1 but regarding my experiences XUP USB-JTAG Programmer is not compatible with Vivado? I tried all ways on Centos-7 OS and the particular script (install_drivers.tar.gz). I aimed to program the Zedboard for petalinux applications developing but no success with XUP USB-JTAG Rev.G and Vivado running on Centos-7. Could you please share any suggestions if you have? Regards. Kursat Gol
  23. Hi there, Iam starting with your cora z7-10 board and I'm little confused with preset file mentioned few times on resource page. I am able to locate XDC master file but not preset file for PS. I am creating my own but I am not able to set voltage on MIO bank 501 to 1.0V as you have in description here on table 2.1 (second section) and I am missing signals like USB resetn... Can you point me to mentioned preset file for PS? Thanks a lot! have nice weekend! Joe
  24. So my current project is very simple, but I've yet to settle on how the control logic is going to be implemented. I think the FSM and Microblaze are both perfectly viable solutions, but I want to find the intersection of maximum learning and minimum complexity. The controller will be performing three tasks: -Pass alternating I and Q data from another module via usb to the user. -Receive data from the user via usb to set a desired frequency. -Interface with the clocking manager to request the new frequency. I am sure I could create an FSM to accomplish this, the USB controller has already been done, my hesitation is a lack of understanding of the AXI4 and DRP interfaces. I am familiar with 8-bit RISC AVR microcontroller, and if given a similar structure, I would think designing with a microcontroller would be almost trivial, but there is surely a learning curve to climb. The question boils down in my mind to a balance between the complexity of the FSM and the learning curve of Microblaze. I also am inclined to say some introductory experience with Mircroblaze would likely be desirable for a future employer. What do you think would be a better opportunity for learning?
  25. This issue had been a pain ever since I started using the CMDO-A7 devices. In Windows 7, using Vivado 2016.2, if I open the hardware manager in Vivado to configure the device, after a few minutes Vivado decides that the target is no longer available and disconnects it. This is a particular problem when I am also using the USB UART... though the problem doesn't happen immediately. This issue makes using the ILA extremely difficult to impossible with this board. When I use the Adept Utility for Windows to configure the board I can use the UART all day without a problem. I suspect a JTAG/UART driver related issue is to blame.