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  1. Hello, I am working with ZedBoard. I have created a custom IP using Vivado for my project. I have tested the working of my custom IP by setting the registers using "Xil_Out32 function (Xilinx SDK baremetal application)" . I have also stored output data of my custom IP to text file on the SD card (using xilffs). Now my objective is to create a petalinux project and implement similar functions(how I have used in baremetal). I dont know how to use Xil_out and xilffs library functions in petalinux. According to my understanding these are specifiaclly used in baremetal application. (in Xilinx
  2. Hi Everyone, Just accidentally flashed the EEPROM attached to the FT2232 device on the Arty. The board is dead without the USB connection. Been using for 2 months without issues until today. In Vivado it is showing: "ERROR: [Labtoolstcl 44-469] There is no current hw_target.". when trying to Auto Connect with the target in Hardware Manager. Within FT_Prog (FTDI's flash tool), the registers (e.g. serial number, vendor ID, D2XX/VCP driver ...) can all be read and modified. How can it be restored back to Digilent factory setting? Is there an FT_Prog template that we can
  3. so i created this project , to display the video from camera OV7670 through VGA on my Zedboard , only using the PL part , the synthesis runs good but i when i try to generate the bitstream i get these errors that i can't seem to understand : error 1 : [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc fil
  4. Hi all, this is my first time posting here because I really need the 2019.4 version of the Xilinx Vivado SDK. I deleted it when I updated to the 2020.2 version today forgetting everything I have would be uncomeatable. I went to redownload the 2019.4 version but only the 2019.1 version was available on the website, this also didn't work. (https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive.html) If anybody has it installed or knows where I could get it I would be grateful. I was also wondering if anybody has a contact at Xilinx that
  5. Hi im getting these warnings while i try to validate design in Vivado while executing hello world program which makes use of Zynq 7000 boards. i kindly request you to give a siolution for these warnings [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values. [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.033 . PS DDR interfaces might fail when entering negative DQS skew values.
  6. Hello All, I am not at all experienced in FPGAs, the only thing I did is in ALTERA in bachelor studies course and recently the Xilinx Zybo board and made a LED blink or a full-adder examples. I am however finding it difficult and frustrating to try to program the flash memory in the Zybo board to make my code non-volatile, after many trials and looking at other examples that do not describe this process step by step there is only ending up quitting. i came across things like FSBL (First Stage Boot Loader), along with the bit stream from Vivado project, then i wanted to avoid th
  7. Hello all: we are using FT2232H on our boards to emulate the JTAG cable such it is recognized by Xilinx tools, ISE and Vivado. The most convenient solution is to use the Digilent driver which is already provided with Xilinx tools. I wonder what is the exact configuration of the FT2232H to enable using this driver? Could you please share the details? Thank you, Wojtek SkuTek Instrumentation
  8. My Basys3 board is not recognized in Vivado. I installed Vivido v2020.2 with little effort (although it took well over an hour). When I connect the USB cable and turn the power on nothing happens inside of Vivido. My board is jumpered for JTAG using JP1 (center pins). If I view the hardware manager it shows "unconnected No hardware target open". Clicking Open target than auto-connect shows no change. Only localhost (0) connected is listed. In Windows10 device manager, I do see 2 USB entries labeled "Digilent USB Device" with a value of, Dual RS232-HS (interface 0) and Dual RS232-HS (
  9. Good Afternoon Sir/Madam, I am trying to display the internal temperature of my device on a four 7-segments anodes hexadecimally. In my attached archive, I have already instantiated the XADC. After going over the user manual of 7 Series FPGAs and Zynq-7000 SoC XADC, Here is what I already know: I am aware that the measured temperature value is in address 00h. I am aware that channels 4 to 0 need to be all zeros to measure the on chip temperature. I am aware that the first 64 access locations (DADDR[6:0] = 00h to 3Fh) of DRP are read only which contain the ADC measureme
  10. rob2018t

    Arty Z7 and Reset

    Hello fellow Digilent Members, I hope everyone is well. My Skill Level: I'm slowly progressing my knowledge of FPGA and Vivado using the Digilent Arty Z7-20 and Arty S7-50. Essentially quite a beginner and I've created simple RTL designs to flash LEDs, utilised the Microblaze, Zynq and made a AXI-4 IP block. All really exciting stuff IMO...I just need to make something more useful now. My Question: when designing with the Arty S7-50 I'm able to specify the board and then drag across the reset into my top diagram and/or utilise that when auto completing the design. However in the
  11. Hi all! I am thinking of purchasing a genesys 2 Board which has a kintex-7 part on it. I have 3 FPGA boards (started with a small lattice board, then a medium altera board, then got a new laptop and a zynq board) and want to move up significantly from the Arty z-7 (which is still a great board) for some of my projects. The problem is, Im wondering if some FPGAs are too much for some computers with not enough resources? specifically Im worried about synthesis and implementation time. If you put the same design on different sized chips, does the larger chip take longer to synthe
  12. this is my first attempt to program an FPGA (I use Basys 3), and when I tried to connect to the hw_server after generating the bitstream , I got this error:
  13. I would like to integrate PMOD NIC100 with Microzed board with Zynq 7020 running on linux. I have a SPI interface routed through the PL logic. Are there any IP that can be directly imported to Vivado for this ? OR Are there any drivers that can be installed on the linux ? Please suggest.
  14. Hello, I've been doing a few beginner experiments with AXI peripherals and following some tutorials online on how to create AXI peripherals and implement on my Kintex board. So far, I've managed to successfully create a simple custom hardware block and connect it via AXI4-Lite. For counter program, Created a new design on Vivado includes AXI Stream data FIFO, AXI Stream FIFO, microblaze and aurora, and through in XSDK, I wrote C codes for counter program and executed. Its working Fine. Help : I need to add DMA into the counter design. So, How can i connect DMA with mic
  15. In all example project I could found, rgb_led is driven from a GPIO block. That works well but I need to drive it from a row of XOR gates and so far I could not convince Vivado to connect the output of the XOR to rgb_led. If you look at the attached picture, the goal is to connect "Res" or "BUFG_O" to rgb_led (which seems to have a 12 bit input since the GPIO which was driving it in the sample project is 12 bit wide). Does anyone know how to do ?
  16. davec

    Problems with MIG_7

    Has anyone had problems trying to use MIG_7 in their block diagrams in Vivado? I had a design that was working under version 2015.3, then something went wrong. Whenever I try to select that IP block in my diagram, vivado hangs trying to open it. I tried deleting it from my design and bring in a new mig_7series block from my list of board components and it hangs as well. I brought my design over onto a different Win7 computer and did a fresh install of a newer vivado 2017.3 with the latest board files with the exact same result- when I try to bring in the mig block, vivado hangs forever.
  17. Hello Digilent Forum! I have been able to run the Cmod A7 Out of Box Demo and export it to an SDK/Vitis project, then modify memorytest.c to write and read new data to and from the SRAM. What a great demo for getting started with the Cmod A7! However, I would like to configure the external memory controller (AXI EMC) block to use its individual ports -- without using the Cmod A7 board file and the "cellular_ram" port from the EMC_INTF pin of the EMC block. I created a new project that uses the xc7a35tcpg236-1 FPGA (not the board file), edited the constraints XDC file, and pinn
  18. Hello everyone! I have ordered my first FPGA. I think I understand VHDL (I have been reading some books about it). My problem is with the toolchain. I don't understand how to use Vivado properly, and the information I find online is really confusing and frustrating. Digilent's tutorial about Vivado is good, but doesn't really get into a lot of detail. What is a good resource for learning Vivado? I would love to know the syntax of constraints, how IP cores really work, how to simulate and testbench, how to analyze the generated hardware properly... Thank you very much!
  19. Hey, I have a very novice question and really just need a high level answer, but I'll get straight to the point! I'm using the Zybo z7-10 with Vivado and Vitis 2019.2. This is what I would like to do, and I'm trying to do it in VHDL: Write some data from software to control registers that I define Perform some processing on this data Use DMA to write some results to DDR I would like the firmware piece that does the processing to be a block in the BD. I've gone through many forums, and it seems at one time the preferred way was to package an IP. I found out about
  20. Dear Sir, I would like to re-create the zmod_adc_dac vivado project. I have follow this link But it seems can not recreate the Vivado project. Error below: (more info and please see log.txt) can't read "assoc": no such variable ERROR: [BD 41-1273] Error running post_config_ip TCL procedure: can't read "assoc": no such variable update_assoc_busif Line 6 Best Regards, Paul log.txt
  21. I left my board connected to my laptop and power to the board was abruptly cut off when the laptop died. I tried to connect the board to a different computer and realized that it no longer turned on. The computer's device manager shows that something is plugged in, but Adept and Vivado are unable to recognize that a device is connected. I was planning to restore the board to it's default setting on Vivado by using a .bin file but received the following error message: "ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210292AA77E6A. Check cable connectiv
  22. Hello, I bought the Zybo-Z7-20 eval board. I downloaded the DMA project from repository and it ran fine in the EDK. So, far so good. However, when I started to re-run synthesis, there were error in the synthesis as to could not synthesize the Zynq part. Below is the error message from the synth log. I would appreciate anyone noticing this error showing how to get past it. Seems like I am missing some setup files or folder, not sure what .... ============================ Near the end of Error Log: ============================ couldn't open "i:/Rafi/Dropbox/Engr_con
  23. Hello, I have issues with DDR4 ipcore design in PL part. Also I am using vivado 2019.2 version.I want to redesign and use DDR4 and I want to write and read huge data sets into the DDR4 in vivado as IPCORE but I could not find any resources about how can we create custom ddr4 ip core. Can you helo me about these issues as soon as possible? Thank you. Best Regards.
  24. Hope you all are fine, I downloaded Digilent/Zybo-Z7-20-HDMI from https://github.com/Digilent/Zybo-Z7-20-HDMI I have upgraded the ip's, it was displaying output on monitor. Then I have created the ip of sobel edge detection and added the ip in block diagram. After solving some clocking issues, bitstream has been generated. After launching to sdk, when I Launch on Hardware (System Debugger), output doesn't display. Below is block diagram, please guide me