Search the Community

Showing results for tags 'Verilog'.

More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL







Found 45 results

  1. Hello everybody, I am having a problem with the binary counter v12.0 reset SCLR signal, when implementing the Xilinx University Programme, Lab9 Project 3.1, 2015x (1). Environment: OS: Linux (Arch Linux) Xilinx Vivado 2018.3 Digilent Basys3 develoment board Verilog HDL Problem description: The project works as expected (counts up to 5 minutes, 0,1 second resolution), the exception is the counter reset button (BTNC, U18) is pressed it only stops the counting, when released, the counter is not reset, instead it keeps counting where it stopped. I am using the Vivado IP Catalog for generating the clock signal and the 4 binary counters(2) used on each 7-Segiment display digit. The Verilog code and constraint file are attached. The binary counter configuration: Implementing using: Fabric Output width: 4 [3:0] Increment Value (Hex): 1 Restrict Count (Hex): 4, 5, 9, 9 (7seg from left ro right) Count Mode: UP Clock Enable (CE): Checked Synchronous Clear(SCLR): Checked Init Value:(Hex): 0 Synchronous Controls and Clock Enable(CE) Priority: Sync Overrides CE Latency Configuration: Manual, 1 Feedback Latency Configuration: Manual, 0 I suspect I am overseeing/forgetting somewhere a simple detail. Any help/clarification is appreciated. Cheers, Rafael. (1) (2) lab9_3_1.v Basys-3-Master.xdc
  2. Hi All: I'm fairly new to both Verilog and the Basys3 board. I'm working thru a 'self education' course. I'm having a problem with the following module. I could use any answers/advice I can get. The module, as posted (below) is processed by Vivado properly, loads into the Basys3 board and runs as expected with the LED blinking at a frequency of .7451 Hz. No problems. The example I'm working thru then threw out a 'challenge' of changing the frequency of the blinking LED based on the positions of two switches [1:0]. 1. I added in the additional input - input [1:0] sw 2. I added in the case statement (which is currently commented out) 3. I commented out the original assignment of led - //assign led = clkdiv[26]; The problem crops up immediately with a Verilog error showing on the following line: case(sw) - The error states: Error: 'sw' is not a constant I've spent hours trying various changes...all to no avail. HELP....PLEASE!!!! Thanks Tons! VERILOG MODULE: module clk_divider( input clk, input rst, input [1:0] sw, output led ); wire [26:0] din; wire [26:0] clkdiv; dff dff_inst ( .clk(clk), .rst(rst), .D(din[0]), .Q(clkdiv[0]) ); genvar i; generate for (i = 1; i < 27; i=i+1) begin : dff_gen_label dff dff_inst ( .clk(clkdiv[i-1]), .rst(rst), .D(din), .Q(clkdiv) ); end endgenerate assign din = ~clkdiv; /* begin case(sw) 2'b00: assign led = clkdiv[26]; 2'b01: assign led = clkdiv[25]; 2'b10: assign led = clkdiv[24]; 2'b11: assign led = clkdiv[23]; default: assign led = clkdiv[26]; endcase end */ assign led = clkdiv[26]; endmodule
  3. Hello everyone. Recently I bought the Pmod i2s2: stereo Audio Input and Output module. I got this working with the example project. As part of the exercise I even translated the I2S part from Verilog to VHDL, and it’s working great by tying the output AXIS directly to the input (without the volume control part). digilent pmod i2s2 code My own vhdl equivalent What I’m a bit confused about, and this may be my limited knowledge of FPGA’s, is that everything is handled on the rising edge of the clock. For example in the digilent pmod i2s2 code in line 135 and 136 the rx_data_l and r register are written on the posedge of the axis_clk. So eventually you get the waveform as in the picture. So far I understand this principle clearly. What I don’t get is why this data on the receive side of the axi is read in on the posedge of the axis_clk. In line 83 and 85 the input data of the axis is written to tx_data_r and l. How can this happen correctly, doesn’t the data bus need some time to change the values. Now it seems that the data is written and read at exactly the same time. Now I want to extend this project by writing the samples into blockram and have the same issue. Can you write the address and data on the same clock as the blockram writes the data, or is it better to write the data on the falling edge for example.
  4. NiLo

    Nexys 3 Pmod Nav Problem

    Hi, I am doing a project on Nexys 3 FPGA board and I am trying to connect Pmod Nav in order to display barometric pressure on PmodOLEDrgb. I am in trouble with Pmod Nav. I have created a Controller that reads via SPI Protocol the 24 bits of 3 data registers and then I have divided this result with value 4097 counts/hPa as it is mentioned in LPS25HB, in order to take the absolute pressure in hPa. The final value should be in range of 260- 1260 hPa. The problem is that the final absolute value of barometric pressure, that I take, is 4095, which means that all bits are stored in 3 registers PRESS_OUT_H, PRESS_OUT_L and PRESS_OUT_XL take the value of '1'. The pins that I have connected are SDI, SDO, SPC, CS_ALT. I have no idea on how to deal with this problem. I would appreciate if someone helped me. Thank you Nik
  5. Hello all of you hope you are in a good health I converted my one of the project from vivado 2015.4 to 2017.4 . After changes i successfully synthesize my code but in implementation it give me this type of error(cal_val_inferred_i_1/O[3] to a signal or tied to VCC or GND ) . After analysis i found out that this error is due to less usage of my bits as One of my wire have 20 bits but i only utilized its lower 9 bits . I declare one dummy register and assign this wire on that register but problem is still not resolved Any kind of help in this regard is appreciable . Best, ATIF JAVED
  6. I've coded UART receiver and transmitter separately in verilog and tested them on Basys 3 FPGA board with Tera Term terminal. I want to connect a USB Keyboard with the board and on pressing keys on keyboard, they gets reflected on Tera Term at same time. ToDo: Basys 3 Board receives data from keyboard and then transmits that data to elsewhere (say Tera Term terminal or a Pmod LCD screen) Problem:- Can anyone help me in how to use USB Keyboard with Basys 3 and how can I implement my UART in this. Attechments: UART receiver and transmitter code is attached below. UART_tx.v UART_Rx.v
  7. Hello, As I am a novice to Verilog/SystemVerilog, I am seeking for some guidance regarding writing Verilog logic from purely just a timing diagram. (You may have seen my other posts). For example, if my goal is to implement a logical block that has X inputs and Y outputs for the DUT, and all I am given is a timing diagram that shows the behavior of the input and output signals and how they behave according to the supplied clock. What is the best way to tackle this problem from an engineering perspective? Should I be considering to first simply layout the module with the inputs and outputs and see how the timing diagram behaves and try to implement the logic based off of that? Or should I be first be treating this as a "state machine" and draw a systematic schematic of showing all the inputs and outputs, showing when they should go HIGH or LOW at their certain times? Are timing diagrams usually implemented in a state machine logical flow? Was hoping to gain some knowledge and understanding from the people who are experienced writing Verilog logic based off of timing diagrams and was hoping to see your systematic approach of how it should be implemented as if I was an engineer. Thank You.
  8. I've created a block ram generator(single port ROM) in vivado using a coe file in verilog. I'm able to read the values one at time using continuous statement(able to instantiate rom block once a clock pulse). Here is my snippet: module coedata(clk,rst,a); input clk,rst; output [31:0]a; wire[12:0]addra,out; wire [31:0]douta ; count c1(clk,rst,out); // just gives count in 'out' to access address(addra) assign addra=out; blk_mem_gen_0 your_instance_name ( .clka(clk), // input wire clka .addra(addra), // input wire [12 : 0] addra .douta(douta) // output wire [31 : 0] douta ); assign a=douta; endmodule This is ok. I can read value through instantiating once a clock. But I want to store all these values into 2D wire such as [31:0] a[0:100].I want all the values to be available in one clock pulse.(Just assume we have created a sufficient ROM block) module coedata(clk,rst); input clk,rst; reg [31:0]a[0:99]; wire[12:0]addra,out; wire [31:0]douta ; count c1(clk,rst,out,i); // just gives count in 'out-binary' to access,'i-integer' address(addra) assign addra=out; blk_mem_gen_0 your_instance_name ( .clka(clk), // input wire clka .addra(addra), // input wire [12 : 0] addra .douta(douta) // output wire [31 : 0] douta ); assign a=douta; endmodule It is saying that 'i' is not a constant. Thanks in advance.
  9. can we use output from python code in verilog on pynq board. e.g if we take hdmi in python. Can we process that frames in verilog.? Thanks
  10. elevator program is not working on the board and it is showing simulation properly.i am not getting where the mistake is happend.can you check the program why it is not working on the board.i thought that the mistake is in the elevator is not taking any inputs according to the module. thanks elevator12.txt
  11. 5v dc motor is not rotating when I connect to pmod ja0 and it is working fine when I connected to vcc and gnd in the pmod ja. anyone can help me .. ???
  12. I have a PmodOLED display board connected to the JA header on an ARTY board by Digilent. I am using Verilog and have tried version 16.4 and 17.1. I am using the supplied sample code to write to the display for the first time. When I try to "Program Device" I get the following error message: [Labtools 27-3303] Incorrect bitstream assigned to device. Bitfile is incompatible for this device. Can someone please tell me what the problem may be? Thanks, Dave
  13. tekson


    Hi all, How to implent delay in verilog code? I want to run a led blink code with one second delay using zynq zybo-7-z10 Thanks in advance
  14. I am trying to implement Decimation on FPGA and Matlab For this task i chose following design parameters Filter type=window hamming hamming method filter order=30 decimation factor=10 input sample rate=2Ms/s output sample rate=200ks/s Normalized cuttof =1/decimation factor First i implement it on MATLAB and use this sequence Filter handle filter delay downsample Using above sequence i successfuly implement it on MATLAB For FPGA i use fir compiler core in which i paste the same coefficients that is generated through matlab But the problem i face is fir compiler core directly gives you the decimated output without handling fitler delay so what should i do if want to handle this filter delay in xilinx Fir compiler core sequence Filter-downsample
  15. I'm trying to get the picosoc project working on a CMOD A7. This is a soft-CPU running code directly from an SPI flash chip, hence I want to get access to the N25Q032A13EF440F pins from verilog. Looking at the Schematic and the .xdc file from the board support package, I can find definitions for qspi_cs and qspi_dq[0-4], which are the chip select and data lines respectively. However there is no definition for for the QSPI_SCK net, which connects to the FPGA pins CCLK_0 and IO_L3N_T0_DQS_EMCCLK_14, both of which are not defined in the .xdc file. Is that deliberately so? Cheers Michael Betz
  16. Hi all, A new website is offering FPGA projects and ZYNQ step by step tutorials with full source codes, maybe it is useful :
  17. Hello everyone, I'm using Zybo and i want to create a custom ip. The ip will have two inputs (as registers) that has 32 bits: Let's call them a[31:0] and b[31:0]. And i want to get memory value at a and add b. The calculated value is a new memory address and i want to read value at that address and write it into the third register of ip. But i haven't find a tutorial like this. If there's any, i would like to know it. Thanks for your time.
  18. Hello, I am using xilinx spartan 6 sp6-x9 board in which its led's and switch works on active low logic. Is it possible to convert switch and leds to to active high logic
  19. Once again I'm sorry if I'm asking what can be considered silly questions, but I'm diving into the FPGA world by myself and I'm having serious dificulties finding documentation or examples that fit my questions. I'm using a Cmod A7 and I want to develop a GUI to let the user define some parameters. Through what I've been researching I believe the way to do it is using UART with the micro usb of the board. I've seen some examples of UART implementations, some I found in responses here on the forum, but due to my lack of knowledge it seems to me they lack important things so I could understand them. So I'll ask two questions: 1 - I believe that if I want to let the user change some parameter, that parameter must be a register and I need to know its adress. But how do I define the adress of that register? I haven't been able to find any example for this. 2 - It seems that the Cmod A7 has two UART ports according to the XDC file, so exactly how am I supposed to use them? Will that make a diference from examples like this one? João
  20. hello, i am using cmod a7. i am trying to blink the led at 1 sec delay(using verilog language). please help me with the code and also let me know the frequency we will be using to create delay and at which pin will it be available.
  21. yassinema2018

    Zybo placing error

    i'm trying to make a pwm module that i want to use later with the sdk the module has two 32 bit inputs, the first is pwm up time and the second is pwmperiod the simulation is good but when i tried to implement the design, i had an placing error ( number of unplaced terminals is greater ....) as i understand vivado tries to give the two inputs a port with 64 bits my purpose is to assign a value to them from the sdk i tried declaring them as wires, integers, reg same error module pwm( input clk, input enable, output pwm_out, input [31:0] pwm_val, input [31:0] pwm_period ); the log file is attached , thank you implem_log.txt
  22. Hello This is the second project for me in FPGA for fun. I want to connect external board with 7 seg as a counter, so I put this Verilog code with this XDC file but the output is something error , could you please figure it out? I use common Anode display PMOD XADC pin 1 ---> pin 12 (7 Seg) pin 2 ----> Pin 9 pin 3 ---> Pin 8 pin 4 -----> pin 6 ------------------------ PMOD JB pin 1 ---> pin 11 pin 2----> pin 7 pin 3-----> pin 4 pin 4 ----> pin 2 pin 5 ----> pin 1 pin 6 ---> pin 10 pin 7 ----> pin 5 pin 8 ----> pin 3 Thanks seven.v Master_zybo.xdc
  23. So, I am starting to get these errors during the Place & Route phase WARNING:Par:288 - The signal kbd<0>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<1>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<2>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<3>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<4>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<5>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<6>_IBUF has no load. PAR will not attempt to route this signal. it only started when I added the enb register. It really makes no sense. `timescale 1ns / 1ps module Trigger(trig,trigb,kbd); output trig; output trigb; input[7:0] kbd; reg trigb; reg trig; reg enb; always begin trigb = kbd[7]; end always @* begin case(kbd) 0: begin enb = 0; trig = 0; end 254: begin // line 0 trig = 0; enb = 0; // kbdphase = 1; end 253: begin // line 1 trig = 0; enb =0; end 251: begin // line 2 trig = 0; enb =0; end 247: begin // line 3 trig = 0; enb =0; end 239: begin // line 4 trig = 0; enb =0; end 223: begin // line 5 trig = 0; enb =0; end 191: begin // line 6 trig = 0; enb = 1; end 127: begin // line 7 if (enb) begin trig = 1; enb = 0; end else begin enb = 0; trig = 0; end end default begin enb = 0; trig = 0; end endcase; end endmodule The idea behind this is that the C64's Keyboard has 8 Column lines that get strobed individually. The row lines will return the keys that are pressed on that column (not implemented). Right now it just throws a line (TRIG) when a line goes high. The problem is that the line 7 does not behave like exactly like the others. It can actually go low for other reasons but never after line 6. So I thought to put up an enable pin to be turned on during line 6 period and then this will let line 7 know it can do its job and it can set the enable register go low again. Anyways, the ISE is giving me a terrible time. Also I can't understand why it requires me to set the enb line low on practically every single part of the case statement... otherwise I get it complaining about a possible latch. Do you all notice anything I am doing wrong? Thanks a lot for any help you can provide.
  24. FlyMario

    FPGA Clock

    I am learning how to program a FPGA (spartan) lately. The language I am using is Verilog which is not really important to this question. I have the FPGA connected to my Commodore 64 via Logic Level Converters. And I am having lot of success. I am reading 8 lines from the Keyboard port looking. My verilog is simply looking for a matching value on those lines. No problems at all. But I am curious, how is the logic managing to work when I have not really set up a clocking line. Is the FPGA using main clock to trigger events to move on in the FPGA. For instance, if you have a blocking statement it would seem that in order to get past that block, there must be some clock checking the incoming value before the logic can continue. Is this true? Or am I missing something. Is there a clock in the fpga that is pushing the logic along? Flymario
  25. Hello to everyone, I'm getting the hex data in the processor and I want to print to pmod ssd. I have an incorrect number. How do I decode 8 bits of hex data? I am not good at English,sorry