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  1. After executing the attached code, my EPWave does not give me the required output clock signals as it reaches logic level '1' in the beginning and stays the same throughout the waveform. I would highly appreciate it if someone could help me out by giving a prompt response. Please note: The above Verilog code is executed in a Cadence Xcelium 20.09 simulator. CODE AND TESTBENCH.docx
  2. Hello everyone, So I own a Basys 2 board with spartan 3E FPGA and I am using ISE Design Suite 14.5. I want to create a VGA output with 800x600 resolution and 40Mhz clock so it will have 60Hz refresh rate. I am writing the code in verilog. I have entered exact numbers for horizontal counter, vertical counter, hsync and vsync that are required for operation stated above. However, I am unable to output the VGA signal. I am using two DCMs that can be generated in the ISE design suite, I am using first DCM to multiply 50MHz clk to 100Mhz and then I am using second DCM to divide 100Mh
  3. Hello I am creating a verilog module on the basys 3 board to interface with the Pmod DA3. I have tried running the module with the DA3 connected and wasn't getting any voltage reading. I have my sclk speed at 25Mhz. Below is my current code and screenshots of my test bench and the pmod outputs on an oscilloscope. Any help is appreciated. `timescale 1ns / 1ps module sclk( input clock, input reset, output sclk ); reg[24:0] count = 0; reg sclk = 0; always @ (posedge clock or posedge reset) begin if (reset ==1'b1)begin count <
  4. I have developed a library component with the usual clock input. The component's logic needs to know at what frequency its clock is running at, which of course is unknown at component creation time. Is there a way, in Verilog, to extract a port or a net's frequency at design synthesis time once the block has been connected to an actual clock? To express the frequency as a wire?
  5. Hi! I want to read the output data of a delta-sigma modulation based ADC (AD7402) using NI LabVIEW FPGA. Can you help me by explaining what the Verilog code in the attached datasheet (page 17) does? AD7402.pdf
  6. Hello, this is my first post in this forum. Im working on a project which I should sample data from ADC (ADS5463), and then fft the sampled data and see the results. The sampling clock is 400MHz and my FPGA working with DRY clock coming from the ADC which is 200MHz (fs/2). Im sampling the data with DDR interface using Lattice IP (GDDRX1_RX.SCLK.Aligned Interface), which sampling 12 bit DDR data into a bus of 24 bit (there the 11:0 bits is positive edge data and 23:12 is the negative edge data). Next Im storing this data into 2 FIFOs, one for the positive edge data and another for th
  7. i enter 5V in FFT so maybe the result are just on impulse signal. but actuality my result have unexpected -'128 signals' (263~390 cnt ) why does -128 apear. and how to disapear unexpected value (-128)
  8. Hello, I have recently purchased Zedboard along with Pmods AD1 and DA4. I want to implement Gradient Descent algorithm in the Zedboard using these Pmods with bandwidth more than 100 kHz. To get started, I tried to regenerate a analog signal using the Pmods AD1 and DA4. The experiment is completely explained with block design and output plots in the ADC_DAC_1_compressed.pdf. The SDK C code for acquistion and generation (adc_dac.c) as well as for finding max. working speed of DAC (dac_maxv.c) are atttached. The ADC clk is set to 20 MHz and DAC clk is to 50 MHz. It could be observed fro
  9. Ahmed Alfadhel

    Verilog

    Hi , I want to learn Verilog . What you suggest for me to start with ? Any recommended books , websites or online courses? Thanks
  10. Hi @[email protected] Thanks for your replies to my questions . They are very helpful . I just want to know does it possible to download Verilator on Windows? If not possible , what are the available options for me to download a Verilog Simulator on Windows? Thanks.
  11. I am learning how to operate an FPGA, and I have to input a signal (which in itself is the output of a discriminator), and analyze it through a Basys3 FPGA. Looking at the available ports on the board, I'm guessing that it could be done using the Pmod ports, but even after hours of googling and going through the manuals, I failed to know which data ports to use, and how to read the signal after I've input it through the board. I've got references to some boards, in which GPIO ports are explicitly labelled, but I don't see any such labeling on the Basys3. So, it'd be really helpful if someone c
  12. I am working in an DSP algorithm, I have generated the bitstream for that algorithm and dumped into FPGA basys 3 board (the output of the algorithm is of 16-bit wide and consists of 100 samples). Now, I need to view the waveform with the help of Waveforms software and analog discovery kit. So, how it can be done? Can anybody provide me some video or anyother material that can solve the problem. #So far information obtained# In the material "Basys 3™ FPGA Board Reference Manual Overview" page no. 18, since, my data is of 16-bit wide I have connected pmod pins JB1 to JB4 to analog dis
  13. I'm trying to put my own verilog module into official nexys video hdmi demo, but vivado 2016.4 keeps telling me "missing design sources" and reports error for implementation. I did as Xilinx says, declared a VHDL component then used named association to instantiate, is it better to declare an entity? EDIT: Verilog module(originally a testbench for another project): module testoverlay_0( input wire rst_n, input wire clk, output reg[23:0] RGBOut, out
  14. I'm a sophomore student and new to FPGA. I want to use two Basys2 boards and two pmodrf1 modules to transport messages. I looked for some examples on Internet but failed to find an available code. Could anyone please give me a complete verilog code about this? Now I am only able to create .v files to accomplish my work. If your solution is not in this way, I expect you to show me what to do step by step. Thank you!
  15. Hello everybody, I am having a problem with the binary counter v12.0 reset SCLR signal, when implementing the Xilinx University Programme, Lab9 Project 3.1, 2015x (1). Environment: OS: Linux (Arch Linux) Xilinx Vivado 2018.3 Digilent Basys3 develoment board Verilog HDL Problem description: The project works as expected (counts up to 5 minutes, 0,1 second resolution), the exception is the counter reset button (BTNC, U18) is pressed it only stops the counting, when released, the counter is not reset, instead it keeps counting where it stopped. I am
  16. Hi All: I'm fairly new to both Verilog and the Basys3 board. I'm working thru a 'self education' course. I'm having a problem with the following module. I could use any answers/advice I can get. The module, as posted (below) is processed by Vivado properly, loads into the Basys3 board and runs as expected with the LED blinking at a frequency of .7451 Hz. No problems. The example I'm working thru then threw out a 'challenge' of changing the frequency of the blinking LED based on the positions of two switches [1:0]. 1. I added in the additional input - input [1:0] sw
  17. Hello everyone. Recently I bought the Pmod i2s2: stereo Audio Input and Output module. I got this working with the example project. As part of the exercise I even translated the I2S part from Verilog to VHDL, and it’s working great by tying the output AXIS directly to the input (without the volume control part). digilent pmod i2s2 code My own vhdl equivalent What I’m a bit confused about, and this may be my limited knowledge of FPGA’s, is that everything is handled on the rising edge of the clock. For example in the digilent pmod i2s2 code in line 135 and 136 the rx_data_l
  18. NiLo

    Nexys 3 Pmod Nav Problem

    Hi, I am doing a project on Nexys 3 FPGA board and I am trying to connect Pmod Nav in order to display barometric pressure on PmodOLEDrgb. I am in trouble with Pmod Nav. I have created a Controller that reads via SPI Protocol the 24 bits of 3 data registers and then I have divided this result with value 4097 counts/hPa as it is mentioned in LPS25HB, in order to take the absolute pressure in hPa. The final value should be in range of 260- 1260 hPa. The problem is that the final absolute value of barometric pressure, that I take, is 4095, which means that all bits are stored in 3
  19. Hello all of you hope you are in a good health I converted my one of the project from vivado 2015.4 to 2017.4 . After changes i successfully synthesize my code but in implementation it give me this type of error(cal_val_inferred_i_1/O[3] to a signal or tied to VCC or GND ) . After analysis i found out that this error is due to less usage of my bits as One of my wire have 20 bits but i only utilized its lower 9 bits . I declare one dummy register and assign this wire on that register but problem is still not resolved Any kind of help in this regard is appreciable .
  20. I've coded UART receiver and transmitter separately in verilog and tested them on Basys 3 FPGA board with Tera Term terminal. I want to connect a USB Keyboard with the board and on pressing keys on keyboard, they gets reflected on Tera Term at same time. ToDo: Basys 3 Board receives data from keyboard and then transmits that data to elsewhere (say Tera Term terminal or a Pmod LCD screen) Problem:- Can anyone help me in how to use USB Keyboard with Basys 3 and how can I implement my UART in this. Attechments: UART receiver and transmitter code is attached below.
  21. Hello, As I am a novice to Verilog/SystemVerilog, I am seeking for some guidance regarding writing Verilog logic from purely just a timing diagram. (You may have seen my other posts). For example, if my goal is to implement a logical block that has X inputs and Y outputs for the DUT, and all I am given is a timing diagram that shows the behavior of the input and output signals and how they behave according to the supplied clock. What is the best way to tackle this problem from an engineering perspective? Should I be considering to first simply layout the module with the inputs a
  22. I've created a block ram generator(single port ROM) in vivado using a coe file in verilog. I'm able to read the values one at time using continuous statement(able to instantiate rom block once a clock pulse). Here is my snippet: module coedata(clk,rst,a); input clk,rst; output [31:0]a; wire[12:0]addra,out; wire [31:0]douta ; count c1(clk,rst,out); // just gives count in 'out' to access address(addra) assign addra=out; blk_mem_gen_0 your_instance_name ( .clka(clk), // input wire clka .addra(addra), // input wire [12 : 0]
  23. can we use output from python code in verilog on pynq board. e.g if we take hdmi in python. Can we process that frames in verilog.? Thanks
  24. elevator program is not working on the board and it is showing simulation properly.i am not getting where the mistake is happend.can you check the program why it is not working on the board.i thought that the mistake is in the elevator module.it is not taking any inputs according to the module. thanks elevator12.txt
  25. 5v dc motor is not rotating when I connect to pmod ja0 and it is working fine when I connected to vcc and gnd in the pmod ja. anyone can help me .. ???