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Found 16 results

  1. When running from Xilinx SDK (2018.3) I cannot get the trivial "Hello world output" from my Zybo Z7 board. However I do get the following messages: Connected to /dev/ttyUSB1 at 115200 Initializing... init:done Zybo Z7-20 Rev. B Demo Image This means that I in general can talk to the port that appears in /dev most often as /dev/ttyUSB1 but at times under different number, so the problem is different from just being unable to get serial port working. The port was initially not accessible due permissions but I have worked around by changing them with chmod. I also added myself to dial group by s'udo adduser audrius dialout' . This has no effect. I have created the "Base Zynq" project with Vivado, generated bitstream without any changes to it, exported (Export hardware, include bitstream) and opened SDK using Vivado menu commands under "File" group. In SDK, I asked to create a new application project, standalone platform, "Hello world". I have selected "Program device" in SDK and passed this step without any obvious errors, with progress bar gradually moving as device is programmed. Also, Vivado shows the device temperature correctly. I noticed that when I do the device programming, the demo LEDs stop flashing in all colors. Only red LD13, green LD12 and green LD4 remain on. However when I attempt to run the project from SDK, multiple LEDs start flashing again, indicating that probably a reset has happened. At this point the "Zybo Z7-20 Rev B Demo Image" appears on the SDK terminal (115200 bauds) , so the terminal in general works. Looks like another "debug terminal" for two cores opens in SDK (TFC Debug Virtual Terminal cores 1 and 0) at this point but also remains empty. I have tried to change the stdout in BSP settings, but switching between "ps7_uart_1" and "ps7_coresight_com" results no changes in behavior. I tried to move the jumper JP5 between JTAG and QSP1. The "Demo image" message shows up in QSP1 position. In JTAG position, just nothing appears. I also tried to flash the bitstream from Vivado directly but this did not change anything. I have no problems in getting the output from KCU116 Microblaze after the similar sequence of actions but this is on another host (Window 7). I am using Ubuntu 16 (4.15.0-43-generic #46~16.04.1-Ubuntu SMP Fri Dec 7 13:31:08 UTC 2018 x86_64 x86_64 x86_64 GNU/Linux) I attach SDK logs and synthesis logs. Board files I have downloaded from https://github.com/Digilent/vivado-boards/archive/master.zip. After installing as described in https://reference.digilentinc.com/vivado/installing-vivado/start I was able to find and select the Zybo Z7 - 20 after restarting Vivado. While the board was initially powered by USB 3, I tried the 5 V wall adapter later, no changes. Last think I tried was connecting the pin aux_reset_in of the block rst_ps7_0_50M to constant value 1 in Vivado designer. It looks like reset signal with active low, so, thought, maybe not a good idea to left hanging as it is initially created. Yet was not helpful. Summarizing, looks like the demo image boots, and the card can be accessed and programmed by Xilinx tools, also serial port works, but the "Hello world" from SDK does not run at all or crashes immediately after start. sdk.log synthesis.log
  2. Hello, I was hoping to use your uC32 board to control 4 stepper motor drivers and to provide debug information over serial back to a PC. Unfortunately though the UART routine implemented in HardwareSerial only has a buffered RX implementation and not a buffered TX implementation. This means that at lower baud rates or with larger debug payloads the time to send the data into the serial line can take a rather long time. I looked around online and I can't find any pre-built libraries that implement an IRQ based UART TX Buffer on the PIC32 that would be compatible with the framework supplied by chipkit. I found one but it's based on entirely different compiler and set of libraries so doesn't appear compatible. http://phoenix-mindgame.blogspot.com/2014/09/pic32-uart-transmission-using-tx.html The regular core arduino HardwareSerial library was updated at some point to support a TX buffer, would diligent consider updating the HardwareSerial implementation that comes with chipkit for the uC32 to also support a TX buffer? UPDATE: I managed to implement a TX buffer without too much difficulty, not sure how robust it is though, this fixed my issue by eliminating blocking serial writes. This might be a useful feature improvement you would consider for the future.
  3. Hello, I've been to set up a new Zybo board but I'm stuck with a serial port issue. I built my design with the provided board files in Vivado 2017.4. I tried a simple "hello world" in SDK but only got a bunch of unprintable characters. I have Tera Term set up for 115200, 8-bit, 1 stop, no parity. I tried Putty as well and had the same results. I verified the Vivado project is using UART1 MIO48..49. I intermittently can get the correct initialization message from the preloaded QSPI image, but most times it's unprintable characters. I also tried the pre-built Linux from the 2017.4 Zybo Petalinux BSP with the same result. It's definitely booting, but the terminal output is unprintable characters. Other things to note: * I'm running off USB power. I'm plugged directly into my laptop * Sometimes pressing the Reset button makes the PGOOD LED flicker until power cycled Thank you Richard
  4. Hey Guys, Im trying to connect HC05 Bluetooth module to my arty board. For this reason, first I implemented a serial module to read data, then I connect an HC05 module to the Arty board via Pmode connectors (Pmod jb connectors): set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {UART_TX}]; set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {UART_RX}]; about serial port, I am 00% sure it works properly with baud rate 9600 because I checked it first with a USB port serial communication and it works perfectly. the program is as follow: I send 8-bit data and data value should be shown in bit format on the LED. As I said it works properly via normal USB serial port but it doesn't work with the HC05 module. Does anyone of you have an idea why? here is the VHDL code (as I stated serial interface module works properly with USB port): library ieee; use ieee.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity main is port( CLK : in std_logic; UART_TX : out std_logic; UART_RX : in std_logic; BLUE_LED : out std_logic_vector(3 downto 0); GREEN_LED : out std_logic_vector(3 downto 0); RED_LED : out std_logic_vector(3 downto 0); LED : out std_logic_vector(3 downto 0) ); end entity; architecture behaviour of main is component uart is port (CLK : in std_logic; UART_RXD : in std_logic; UART_DATA_READ : out std_LOGIC_VECTOR(7 downto 0); UART_READ_FLAG : out std_logic; UART_DATA_WRITE : IN STD_LOGIC_VECTOR(7 downto 0); response_is_ready : in std_logic; UART_TXD : out std_logic ); end component; signal clock : std_logic; signal data_send : std_logic_vector(7 downto 0); signal data_receive : std_logic_vector(7 downto 0); signal data_ready_to_send : std_logic; signal data_received : std_logic; signal LED_VALUE : std_logic_vector(3 downto 0); signal UART_RX_S : std_logic:='0'; signal UART_TX_S : std_logic:='0'; signal i_int : integer:=0; type LED_STATUS is (LED_ON,LED_OFF,CHANGE_COLOR,INIT); signal LED_STATE : LED_STATUS := INIT; begin inst_UART:uart port map( CLK => CLK, UART_RXD => UART_RX_S, UART_TXD => UART_TX_S, UART_DATA_READ => DATA_Receive, UART_DATA_WRITE => DATA_Send, response_is_ready => data_ready_to_send ); inst_proc:process(clk,DATA_Receive,LED_STATE) --variable i: integer:=0; begin if(rising_edge(clock)) then GREEN_LED<=DATA_Receive(3 downto 0); LED_VALUE<=DATA_Receive(7 downto 4); end if; end process; CLOCK<=CLK; LED<=LED_VALUE; UART_TX<=UART_TX_S; UART_RX_S<=UART_RX; end architecture; Thx
  5. MVS

    Arty Z7-20 Serial Com

    Hello everyone, I bought an Arty z7-20 board a month ago and my first project depends on serial communication. I made a program in VHDL but I could not know which are the pins that I should assign to the uart. From schematic file, i understand that i have to comunicate the fpga with the pins C5 and C8, for Tx and Rx, on the chip bank500, but.... i dont see what are the pins to enable uart in the .xdc master file to do this. A lot of thanks for share your experience! I leave here a simple design to taste the uart. The idea is that the fpga recive a data and send it back to a terminal. SERIAL_ENSAYO.vhd
  6. Hello, I have been using the WiFire board Rev D for data collection. A data stream is sent from the WiFire board to the windows computer over USB. Programming is via Microchip Blockset for Simulink: http://www.microchip.com/promo/mplab-device-blocks-for-simulink Downloadable code is auto-generated by Simulink (CTRL B to build) Program loading is via Pickit3, the .elf file is attached. This system was working fine, but suddenly the windows system can no longer see the com port. How can I fix this? Thanks, John ChipKit_WiFire_32MZ2048EFG100_Standalone_R2015b.elf One more note: the WiFire board should show up in Windows Device Manager as a com port, and it does not, see screen shot. If I plug in an Arduino, it shows up as COM4, the WiFire should look similar. John
  7. Hello everybody, I am trying to send data from a Windows 10 computer to a Basys 3 board (Artix7 FPGA). I am using UART, and the data is entered via PuTTY, at 9600 bauds, with a stop bit and no parity. My VHDL module is based on a Finite State Machine (FSM), and two internal signals ensure the correct sampling (middle of the received bits). To test my VHDL module, I drive 8 LEDs on the board according to the received data. The problem : I manage to switch on / off the LEDs, but it doesn't seem to correspond to anyting (wrong ASCII code, or no difference between different key inputs...). So it seems I well receive data (TX lits on the Basys 3), but it is not processed correctly, and I cannot find why ! Could you please help me finding what's wrong ? ****** EDIT 1 *********************** I forgot to say that I tried to use another module found on the Internet ( https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html ), without any success (same issue). ******* END OF EDIT 1 ********** Please find hereafter my VHDL code & my .xdc : ## Clock signal set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] ## LEDs set_property PACKAGE_PIN U16 [get_ports data_out[0]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[0]] set_property PACKAGE_PIN E19 [get_ports data_out[1]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[1]] set_property PACKAGE_PIN U19 [get_ports data_out[2]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[2]] set_property PACKAGE_PIN V19 [get_ports data_out[3]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[3]] set_property PACKAGE_PIN W18 [get_ports data_out[4]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[4]] set_property PACKAGE_PIN U15 [get_ports data_out[5]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[5]] set_property PACKAGE_PIN U14 [get_ports data_out[6]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[6]] set_property PACKAGE_PIN V14 [get_ports data_out[7]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[7]] ##Buttons set_property PACKAGE_PIN T18 [get_ports RAZ] set_property IOSTANDARD LVCMOS33 [get_ports RAZ] ##USB-RS232 Interface set_property PACKAGE_PIN B18 [get_ports RxD_in] set_property IOSTANDARD LVCMOS33 [get_ports RxD_in] library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity UART_RX is Port ( RxD_in : in STD_LOGIC; clk : in STD_LOGIC; RAZ : in STD_LOGIC; data_out : out STD_LOGIC_VECTOR (7 downto 0)); end UART_RX; architecture Behavioral of UART_RX is signal tick_UART : STD_LOGIC; -- Signal "top" passage d'un état à l'autre selon vitesse connexion série signal double_tick_UART : STD_LOGIC; -- Signal précédent, fréquence * 2 signal compteur_tick_UART : integer range 0 to 10420; -- Compteur pour tick_UART signal double_compteur_tick_UART : integer range 0 to 5210; -- Compteur pour demi-périodes type state_type is (idle, start, demiStart, b0, b1, b2, b3, b4, b5, b6, b7); -- Etats de la FSM signal state :state_type := idle; -- Etat par défaut signal RAZ_tick_UART : STD_LOGIC; -- RAZ du signal tick_UART; signal RxD_temp : STD_LOGIC; -- RxD provisoire entre deux FF signal RxD_sync : STD_LOGIC; -- RxD synchronisé sur l'horloge begin D_flip_flop_1:process(clk) -- Clock crossing begin if clk = '1' and clk'event then RxD_temp <= RxD_in; end if; end process; D_flip_flop_2:process(clk) -- Clock crossing begin if clk = '1' and clk'event then RxD_sync <= RxD_temp; end if; end process; tickUART:process(clk, RAZ, state, RAZ_tick_UART) -- Compteur classique (tick_UART) begin if clk = '1' and clk'event then if (RAZ='1') or (state = idle) or (RAZ_tick_UART = '1') then compteur_tick_UART <= 0; tick_UART <= '0'; elsif compteur_tick_UART = 10417 then tick_UART <= '1'; compteur_tick_UART <= 0; else compteur_tick_UART <= compteur_tick_UART + 1; tick_UART <= '0'; end if; end if; end process; doubleTickUART:process(clk, RAZ, state) -- Compteur demi-périodes (double_tick_UART car fréquence double) begin if clk = '1' and clk'event then if (RAZ='1') or (state = idle) then double_compteur_tick_UART <= 0; double_tick_UART <= '0'; elsif double_compteur_tick_UART = 5209 then double_tick_UART <= '1'; double_compteur_tick_UART <= 0; else double_compteur_tick_UART <= double_compteur_tick_UART + 1; double_tick_UART <= '0'; end if; end if; end process; fsm:process(clk, RAZ) -- Machine à état begin if (RAZ = '1') then state <= idle; data_out <= "00000000"; RAZ_tick_UART <= '1'; elsif clk = '1' and clk'event then case state is when idle => if RxD_sync = '0' then -- Si front descendant de RxD (= bit de start) et en idle state <= start; RAZ_tick_UART <= '1'; end if; when start =>if double_tick_UART = '1' then -- Demi période écoulée (pour échantillonage) state <= demiStart; RAZ_tick_UART <= '0'; -- Le compteur tick_UART commence à compter end if; data_out <= "00000000"; -- Reset des anciennes données when demiStart => if tick_UART = '1' then state <= b0; RAZ_tick_UART <= '0'; end if; data_out(0) <= RxD_sync; -- Acquisition bit 0 when b0 => if tick_UART = '1' then state <= b1; end if; data_out(1) <= RxD_sync; -- Acquisition bit 1 when b1 => if tick_UART = '1' then state <= b2; end if; data_out(2) <= RxD_sync; -- Acquisition bit 2 when b2 => if tick_UART = '1' then state <= b3; end if; data_out(3) <= RxD_sync; -- Acquisition bit 3 when b3 => if tick_UART = '1' then state <= b4; end if; data_out(4) <= RxD_sync; -- Acquisition bit 4 when b4 => if tick_UART = '1' then state <= b5; end if; data_out(5) <= RxD_sync; -- Acquisition bit 5 when b5 => if tick_UART = '1' then state <= b6; end if; data_out(6) <= RxD_sync; -- Acquisition bit 6 when b6 => if tick_UART = '1' then state <= b7; end if; data_out(7) <= RxD_sync; -- Acquisition bit 7 when b7 => if tick_UART = '1' then state <= idle; -- state <= stop; end if; end case; end if; end process; end Behavioral;
  8. Is there anyone that has a direct link to download just the USB drivers for the Analog Discovery II (not part of Waveforms 2015)? We are having driver issues on Windows 10. We've tried every other solution that we could find on these forums. (Manually pointing to the drivers, rebooting, reinstalling waveforms including the Adept Runtime, etc.) We are looking for JUST the drivers that someone from tech support can send us while trying to fix this problem.
  9. Hello, just plugged in my new Zybo Z7 471-015 but cannot connect to serial port. It works on the Zybo. PROG UART is connected to USB PC BSP stdin, stdout is set to ps7_uart_1 I have no other application open that is accessing the serial ports to make sure I dis- and reconnected the Zybo Z7, still doesn't appear on the port list Zybo Z7 appears as USB Serial Converter A and B in the device mngr restarted PC tried another USB port replaced USB cable, both are data cables JP6 is set to USB JP5 is set to JTAG drivers had been installed with Vivado 2017.2 re-installed Vivado 2017.2 cable drivers, restarted PC USB port should be listed even without any PL configuration loaded, right?
  10. In my project, I need to use the UART ports on the NexysVideo board to transmit signals to a Raspberry. I defined 2 signals Rx_raspi as an in std_logic and Tx_raspi as an out std_logic, and in the XDC file, they are defined as: set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports Rx_raspi ]; set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports Tx_raspi ]; while implementing, errors show that no ports matched. [Vivado 12-584] No ports matched 'Tx_raspi'. [Vivado 12-584] No ports matched 'Rx_raspi'. [Common 17-55] 'set_property' expects at least one object. [Common 17-55] 'set_property' expects at least one object. What was wrong?
  11. Hi, I just bought the Analog Discovery 2 and I was looking for a way to generate serial data(uart, spi) to test my projects through the digital output pins. I was wandering since there is a logic analyser and interpreters for serial communication data. Thanks for you help
  12. Hi! I've got an ARTY board and I find the USB connection incredible useful, as it allows to use only one connection to program the FPGA through JTAG while simultaneously act as an USB to serial converter. So, I also bought a JTAG-SMT2-NC to fit into a custom board and it's a very convenient way to program my FPGA, but... is it possible for it to act as the module that fits on the ARTY, and make it be recognized by the PC as a USB-serial converter, using its GPIO pins as the interface with the FPGA, as the ARTY does? That would be really great, but I think it's not possible, is it?
  13. swarnava

    Using PMOD Modules

    Hi, I'm using a Deca MAX 10 FPGA evaluation kit. I want to transfer the data from my evaluation kit to my system and vice-versa, but the Kit only has USB OTG but no UART module so I'm thinking of connecting a PMOD USB to UART module to the GPIO pins in my kit for making the transfer possible. Is it possible to convert the GPIO pins to the PMOD pins in order to connect the PMOD module ? Can anyone please help me in this ? Thanks, Swarnava Pramanik
  14. How to setup diligent usb cable for Xilinx Spartan-3 starter kit on CentOS 6? I have already installed ISE WebPack, digilent.adept.runtime, digilent.adept.utilities, libCseDigilent, fxload, and some other packages. lsusb shows: [lukasz@localhost home]$ lsusb Bus 001 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub Bus 001 Device 006: ID 03fd:000d Xilinx, Inc. but djtgcfg shows nothing: sudo djtgcfg enum No devices found iMPACT log: Welcome to iMPACT iMPACT Version: 14.7 Project: /home/lukasz/VHDL/QLIW//auto_project.ipf created. // *** BATCH CMD : setMode -bs // *** BATCH CMD : setMode -bs // *** BATCH CMD : setMode -bs // *** BATCH CMD : setMode -bs GUI --- Auto connect to cable... // *** BATCH CMD : setCable -port auto INFO:iMPACT - Digilent Plugin: Plugin Version: 2.4.4 INFO:iMPACT - Digilent Plugin: no JTAG device was found. AutoDetecting cable. Please wait. *** WARNING ***: When port is set to auto detect mode, cable speed is set to default 6 MHz regardless of explicit arguments supplied for setting the baud rates PROGRESS_START - Starting Operation. If you are using the Platform Cable USB, please refer to the USB Cable Installation Guide (UG344) to install the libusb package. Connecting to cable (Usb Port - USB21). Checking cable driver. File version of /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusbdfwu.hex = 1030. File version of /etc/hotplug/usb/xusbdfwu.fw/xusbdfwu.hex = 1030. WinDriver v10.31 Jungo (c) 1997 - 2011 Build Date: May 24 2011 x86_64 64bit 18:13:19. Cable connection failed. Connecting to cable (Parallel Port - parport0). WinDriver v10.31 Jungo (c) 1997 - 2011 Build Date: May 24 2011 x86_64 64bit 18:13:19. Cable connection failed. Connecting to cable (Parallel Port - parport1). WinDriver v10.31 Jungo (c) 1997 - 2011 Build Date: May 24 2011 x86_64 64bit 18:13:19. Cable connection failed. Connecting to cable (Parallel Port - parport2). WinDriver v10.31 Jungo (c) 1997 - 2011 Build Date: May 24 2011 x86_64 64bit 18:13:19. Cable connection failed. Connecting to cable (Parallel Port - parport3). WinDriver v10.31 Jungo (c) 1997 - 2011 Build Date: May 24 2011 x86_64 64bit 18:13:19. Cable connection failed. PROGRESS_END - End Operation. Elapsed time = 2 sec. Cable autodetection failed. WARNING:iMPACT:923 - Can not find cable, check cable setup !
  15. I was looking at the PmodUSBUART, PmodRS232, PmodRS232X and the Digilent Pmod Interface specification and need some clarifications The PmodUSBUART and PmodRS232X uses the Type 4 Pinout and the PmodRS232 uses the Type 3 Pinout. The table pinout on the Pmod Interface Specification is for the Host for Type 3 and Type 4 UARTs. Can someone verify that my assumptions are ok?
  16. asmao

    PMOD as GPIO

    Hello, I'm currently using a Nexys 4 board and I would like to serially output and receive data. I was wondering if this could be done through a PMOD port? If so, how? Inside of my HDL design (I'm using Vivado 2014.2 and my HDL is in verilog) I'm asserting various PMOD ports yet whenever I try to measure the outputs I got nothing. My HDL looks something like this:assign JC1 = 1, JC2 = 0; Both JC1 and JC2 measure to 0. I've also tried the alternative names listed in the schematics (K2 and E7) as well as other PMOD interfaces. If I can't use the PMOD ports in this fashion, I was hoping to hear any suggestions? Thanks,Alvin