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  1. This projects implements a custom function generator (FuncGen) implemented in VHDL on Nexys 4 DDR board using PmodDA4 and PmodAD2. Command signal to the function generator is supplied from Matlab through on-board UART bridge as a 16-bit long command word (unsigned integer). Digital command signal is converted into corresponding voltage signal by DAC (Pmod DA4), which can be used to drive external device. Feedback, implemented on the ADC (PmodAD2), allows user to read the actual level of the voltage signal. The feedback signal is sent back to the DTE (PC, Matlab), using the same UART bridge. Note, that ADC used external reference voltage of 2.5V to match the reference voltage of DAC. The current level of the voltage feedback signal is displayed on the on-board 8-digit seven segment display. a2d.vhd brgen.vhd clock.vhd dig2an.vhd disp.vhd fbin2bcd.vhd func_gen.vhd ibin2bcd.vhd rx.vhd ssd.vhd tx.vhd Nexys4DDR_Master.ucf func_gen.m
  2. Hello, dear collegues! I work with Nexys Video board. I use VHDL. Now I try to create project with PmodDA4. I have 4 variables which I obtained inside the project and I want to obtain it like 4 analog signals. I have found an example, but when I tried to implement it for my board it does not work (code is bellow)... If it is some example code for this PmodDA4, please send it... I could not find it for this board. -- The four left-most switches (SW15-SW12) define the command, i.e. 0011 -- The four switches after (SW11-SW8) define the address, i.e. 1111 -- The right-most switch (SW0) defines the regime: working, fast (0) or "human", slow (1) library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity pgnd is port( btnc : in STD_LOGIC; sysclk : in STD_LOGIC; sw : in STD_LOGIC_VECTOR(7 downto 0); led : out STD_LOGIC_VECTOR(3 downto 0); jb : out STD_LOGIC_VECTOR(3 downto 0) ); end pgnd; architecture pgnd of pgnd is signal count: STD_LOGIC_VECTOR(27 downto 0) := X"0000000"; signal count2: STD_LOGIC_VECTOR(11 downto 0) := X"001"; signal word_count: STD_LOGIC_VECTOR(5 downto 0) := "000000"; signal sclk0, pout: STD_LOGIC; signal sync0 : STD_LOGIC := '0'; -- signal data: STD_LOGIC_VECTOR(11 downto 0) := X"000"; signal pdata: STD_LOGIC_VECTOR(31 downto 0) := X"00000000"; begin counterp: process(sysclk, btnc) begin if btnc = '1' then count <= X"0000000"; elsif rising_edge(sysclk) then count <= count + 1; end if; end process; sclkp: process(sysclk, count, btnc) begin if btnc = '1' then sclk0 <= '0'; elsif rising_edge(sysclk) then if sw(0) = '1' then -- Use the same freq for both LEDs and sync sclk0 <= count(25); -- Divide 100 MHz / 2^25 => "human" freq else sclk0 <= count(5); -- Divide 100 MHz / 32 = 3.125 MHz end if; end if; end process; -- Word bits counter: 40 = 32 bits sync + 8 void bits word_countp: process(sclk0, btnc) begin if btnc = '1' then word_count <= "101000"; -- # 40 elsif rising_edge(sclk0) then if word_count = "101000" then word_count <= "000000"; else word_count <= word_count + 1; end if; end if; end process; -- Sync signal signal_syncp: process(sclk0, word_count, btnc) begin if btnc = '1' then sync0 <= '1'; elsif rising_edge(sclk0) then if word_count = "000000" then sync0 <= '0'; elsif word_count = "100000" then sync0 <= '1'; end if; end if; end process; signal_shiftp: process(sclk0, word_count, sw, count2, btnc) begin if btnc = '1' then pdata <= X"0" & sw(7 downto 0) & count2 & X"00"; elsif rising_edge(sclk0) then if word_count = "101000" then pdata <= X"0" & sw(7 downto 0) & count2 & X"00"; else pdata <= pdata(30 downto 0) & pdata(31); end if; end if; end process; -- Sawtooth data modulation data_countp: process(sclk0, word_count, btnc) begin if btnc = '1' then count2 <= X"001"; elsif rising_edge(sclk0) and word_count = "101000" then count2 <= count2 + 1; end if; end process; -- Data transmission process spip: process(sclk0, word_count, btnc) begin if btnc = '1' then pout <= '0'; elsif rising_edge(sclk0) then -- Send the signal pout <= pdata(31); end if; end process; JB(0) <= sync0; -- SYNC JB(1) <= pout; -- DOUT JB(2) <= pout; -- Just duplicate DOUT JB(3) <= sclk0; -- SCLK led(0) <= sclk0 when sw(0) = '1' else -- show the real SCLK count(24); -- or indicate device is working on higher freq led(1) <= sclk0 when sw(0) = '1' else not count(24); -- Couple the other leds only if the frequency is "human" led(2) <= pout when sw(0) = '1' else '0'; -- DOUT led(3) <= sync0 when sw(0) = '1' else '0'; -- SYNC end pgnd;
  3. Hello. I found similar question “Working with DA4 PMOD on Nexys 4” posted on 23 Oct. 2014 and answer from JColvin. I understand the hint about usage of internal voltage. Nevertheless I don’t see output voltages. It is not easy to me to follow applied code, because I have learned so far Verilog and example is given in VHDL. I am electrical engineer and programmer by education, but I am new to digital electronics and FPGAs. I have acquired some initial experience by learning book “Digital Design Using Digilent FPGA Boards. Verilog/ Active –HDL Edition” by Richard E.Haskell and Darrin M.Hanna from 2012. I have implemented many examples from the book on BASYS2 board that I have. Now I would like to see voltages on outputs of PmodDA4 that I connect to my BASYS2 board. For beginning I will be satisfied with direct (permanent) voltages. I have been trying few versions of code and didn’t succeed. Please, advise – what is wrong? May be many things… I will try to describe my logic in details and attach my code too. I use Verilog. I connect PmodDA4 to JA connector of BASYS2 board. I have to create 3 correct signals: SYNC, DIN and SCLK. According to documentation I assume that: 1. SYNC: JA1 (B2) – pio<72> in ucf file. 2. DIN: JA2 (A3) – pio<73> in ucf file. 3. SCLK: JA4 (B5) – pio<75> in ucf file. Default frequency of a board is 50 MHz. I use half of this frequency – 25 MHz as a SCLK signal. I understand logic of operation so: if SYNC is high – data from signal DIN does not go into internal register of PmodDA4. After SYNC went low – data starts to go into internal register of PmodDA4. It goes into PmodDA4 on each negedge of SCLK and it counted by PmodDA4. By data we mean signal DIN: 0 or 1. After transferring 32 bits into internal register of PmodDA4 we have to change SYNC on high. May be that not necessarily to do right away after 32 accumulated bits, but I do that in my code, because in any way we must bring SYNC high for min 15 ns and after low for initiation of a new cycle of writing data into internal register of PmodDA4. I control that process by variable count. I simulated the process with Aldec simulator and visually it seems to me correct. I assume that bit db31 on a page 7 of is a first bit in time among 32 bits that is clocked into internal register of PmodDA4. Here is a sequence of 32 bits that I try to produce, taking JColvin’s notice about using Internal source of power. Don’t care bits db31, 30, 29, 28: 0000. Command bits db27, 26, 25, 24: 1011. Address bits db23, 22, 21, 20: 1111 – command for having voltage on all 8 outputs. For AD5628 12 bits db19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8 equal to 1 for max output voltage: 111111111111. And last 8 bits db7, 6, 5, 4, 3, 2, 1, 0: 00000001. As I understood your notice bits db27 and db0 have to be 1 – for using internal voltage as a source. My code for the project is attached in file Basys2_PmodDA4_code.txt. Basys2_PmodDA4_code.txt
  4. Hi, I was working with the PmodDA4 to get it up and running, but was having trouble to get it to work since I didn't know how the 32 bit Word the reference manual claimed I needed to send was supposed to look like.
  5. Hello! If you have ever used something that produced sound through a speaker, than you have indirectly used a Digital-to-Analog Converter, or DAC for short. Many tutorials on how to use a DAC will cover how to use a R-2R resistor ladder which is one of the popular ways that DACs are constructed. However, not very many explain how you might use a DAC that is already created in a small IC chip, such as the one present on the PmodDA4. But no more! You can learn more about DACs in general from the Digilent Blog as well as how to use an IC DAC from this Instructable.