Search the Community

Showing results for tags 'PmodAD1'.

More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments and the WaveForms software
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL







Found 6 results

  1. Hey all, First off, I apologize - I'm at work, now, with no access to the hardware, o-scope, etc. So all from memory for now, until I can get some time at home.... NOTE: All development being done under Xilinx ISE 14.7 WebPack. Target platform is an Opal Kelly XEM3005 (Xilinx Spartan 3E) Day 1: Wrote & sim'd Verilog to drive a PMODAD1 12b ADC. Seemed to work as planned. Day 2: Tried interfacing to an Opal Kelly XEM3005 (Spartan 3E) board with 3.3V logic & power. No joy. Funky stuff going on. Began troubleshooting. Day 3: Wrote code for Raspberry Pi Zero W (using WiringPi) to drive the AD1. Everything works as it should. Data reads work as close to perfect as I can ask for. Day 4: Continue troubleshooting FPGA - realize my constraints file is no bueno, and is assigning FPGA pins incorrectly. Fixed that. (So, reasonably sure that constraints file is copacetic) Day 5: Wrote code to drive a PMOD DA2 2-channel 12b DAC. Code Sim'd. Works well. Integrated into FPGA - code works well, DA2 works as advertised. Also works well with OK's FrontPanel - I can give a command from the PC, and the DA2 spits out the appropriate voltage. (This was another step to validate FPGA platform functionality & correctness). Day 6: Re-code and re-sim DA1 Verilog. Works as expected. Day 7: Integrate code onto XEM3005 - still no joy. Probe with oscilloscope: Power good - 3.3V, rock solid Ground good: little to no noise. Chip Select (CS) looks good - ~990kHz rate, normally high, Goes low for readout periods. Less than perfect due to being on a protoboard connected via a 6: cable. Serial clock (SCK) looks good - ~16MHz, only active during CS Low periods, high when CS is high (quiet time) DO and D1 outputs - constant low. A fair amount of digital noise. Sometimes, having a probe attached to D0 or D1 with the other probe attached to SCK or CS will couple noise in to the FPGA, giving me a noisy signal that is meaningless (except for the fact that it tells me my inputs are working - or so I think) It appears as though (bare with me - I'm an analog guy) the lines are heavily loaded - i.e., something is pulling the lines to ground. I see on the AD1 datasheet that the outputs are protected by 100 Ohm resistors, so this seems a potential (likely?) culprit (?) Not instantiating IOB's in my code, but those normally aren't necessary except to override defaults in the constraints file. Double- and triple-checked that the D0 and D1 ports are set up as inputs. Constraints file does not explicitly turn on Pull-ups or pull-downs. (LOGIC_3v3, IIRC) Recoded main fixture to move connections to different pins. No change in results - everything (appears) identical. Day 8: Just got home - did some double checking and disconnected the PMOD outputs from the FPGA: With the FPGA disconnected, the signals look pretty darned good: Took some quick measurements of the FPGA input pins - they seem to hava a constant ~0.75V on them with quite a bit of digital trash... This is clearly (I think) an FPGA setup problem.. So, here I am... Looking for clues. Anyone have any? Thanks in advance
  2. Dear All, I am trying to get two signals in the pmodAD1 simultaneously and send the data through the two channels in the pmodDA2 simultaneously. I got the code working for a single channel and I tried to modify it for two of them. However, even though the compilation does not give me any error, I do not see any signal out of the pmod in the oscilloscope. Please, find attached the piece of code. Any help or suggestion will be really appreciate it! Thanks a lot! 2channel main.txt 2channel pins.txt
  3. Hello to all, I am looking for help resolving a conflict between two Pmods. The Zybo board is configured in standalone (bare metal) mode. Each of Pmods was tested and worked perfectly well when running alone. It should be noted that RTCC module works also with the Pmod OLED without any issues. However, when I add PmodRTCC to the system it hangs. Debugging indicated that is does have address but no pointer to the myDevice struct. Attached is a block diagram of the system. I am sure that I missed something and hoping that people will spot it quickly. Thank you!
  4. hi, I am using PMOD AD1 and PMOD DA2 on ZC702 Eval Board but it dose not work. Befor that I used my code with spart 3a, spartan6 and zedboard and my code work for all of them but when I used that code for the zc702 it dose not work. I use clock division to send 20 Mhz : This is my code: library ieee; use ieee.std_logic_1164.ALL; --use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.ALL; use ieee.numeric_std.all; Library UNISIM; use UNISIM.vcomponents.all; entity ad1_da2 is port( SCLK_P : in std_logic; SCLK_n : in std_logic; CS : out std_logic; -- chip select for ADC(active low) SYNC : out std_logic; -- SYNC for DAC DIN : in std_logic; -- ADC DOUT : out std_logic; -- DAC SCLK : out std_logic; -- ADC SCLK2: out std_logic -- DAC ); end ad1_da2; architecture Behavioral of ad1_da2 is component IBUFGDS is port ( I : in std_logic; IB : in std_logic; O : out std_logic ); end component; -- FSM states type state_type is (IDLE, READ_DATA, FUNC, WRITE_DATA); -- initial state signal state : state_type := READ_DATA; -- data from the ADC signal data : std_logic_vector(11 downto 0); -- counter variable signal cnt : integer range 0 to 20 := 0; -- counter for clock division signal clkdiv : integer range 0 to 10; -- new clock from division signal newclk : std_logic := '0'; signal risingedge : std_logic := '1'; -- reset signal signal reset : std_logic := '0'; signal clk : std_logic; begin SCLK <= newclk; SCLK2 <= newclk; begin if (reset = '1') then elsif (rising_edge(CLK)) then if (clkdiv = 10) then -- divide 200MHz by 10 risingedge <= risingedge xor '1'; newclk <= newclk xor '1'; clkdiv <= 0; else clkdiv <= clkdiv + 1; end if; end if; end process clock_divide; main : process (CLK, reset) begin if (reset = '1') then elsif (rising_edge(CLK)) then if (clkdiv = 10 and risingedge = '1') then case state is when IDLE => CS <= '1'; SYNC <= '1'; if (cnt = 16) then cnt <= 0; state <= READ_DATA; else cnt <= cnt + 1; state <= IDLE; end if; when READ_DATA => CS <= '0'; SYNC <= '1'; cnt <= cnt + 1; if (cnt<4) then cnt <= cnt + 1; state <= READ_DATA; elsif (cnt > 3 and cnt < 16) then cnt <= cnt + 1; -- the first 4 bits are 0000 only read the last 12 data(15-cnt) <= DIN; state <= READ_DATA; elsif (cnt = 16) then cnt <= 0; state <= FUNC; end if; -- signal processing would go in this state -- but for now we don't do anything in here when FUNC => CS <= '1'; SYNC <= '1'; cnt <= 0; state <= WRITE_DATA; when WRITE_DATA => CS <= '1'; SYNC <= '0'; if (cnt = 0 or cnt = 1) then cnt <= cnt + 1; DOUT <= '0'; state <= WRITE_DATA; elsif (cnt = 2 or cnt = 3) then cnt <= cnt + 1; DOUT <= '0'; state <= WRITE_DATA; elsif (cnt > 3 and cnt < 16) then cnt <= cnt + 1; DOUT <= data(15 - cnt); state <= WRITE_DATA; elsif (cnt = 16) then cnt <= 0; state <= IDLE; end if; end case; end if; end if; end process main; ibufgds_0 : IBUFGDS port map ( I => SCLK_P, IB => SCLK_n, O => CLK ); end Behavioral; Do you have an idea?
  5. Dear All, I am planning to program a PID controller on the Basys3. For this purpose, I first tried to get a signal from a function generator into the ADC (pmodAD1) and output it through the DAC (pmodDA2). This works fine. I wanna take the digital output of the ADC, multiply or divide it by a real factor and output the result through the DAC. There might be better ways of doing this but in order to specify the re number, I have created two integer numbers and apply a division between them. This would allow me to get any "real" number that I want. constant mul_number : integer := 5; constant div_number : integer := 4; signal mul_number_unsigned : unsigned(11 downto 0); signal div_number_unsigned : unsigned(11 downto 0); mul_number_unsigned <= to_unsigned(mul_number,12); div_number_unsigned <= to_unsigned(div_number,12); when mul_number_unsigned/div_number_unsigned = integer : the voltage height increases according to the set value. when mul_number_unsigned/div_number_unsigned > 1 and real : nothing happens to the signal and the same input signal is output again. when mul_number_unsigned/div_number_unsigned < 1 , positive and real : the is no output signal. I do not know how to solve the problem since the compiling does not give me any warning or error...Any help or suggestion would be really appreciated. Thanks a lot! PS: sorry for the code file format but the system did not allow me to upload a .vhd file. acd_func_dac.txt
  6. hi, we are trying to read data from 4 wire resistive touch screen. can any one help us figuring this out? We have the voltage reading from touch screen, we don't know exactly how we code that reading to Pmode and implement it to nexys3. help will be appreciate!!!