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Found 65 results

  1. Hello, I am currently working on a project using the Zedboard and some Pmods from Digilent. As of now, I have booted Ubuntu 16.04 onto the ARM core using the Petalinux tools through an SD card. I have also been looking into the GPS pmod and got the bare-metal example to work from programming the FGPA. Through my personal computer (Ubuntu 18.04), I have been able to interface with the Ubuntu 16.04 on the ARM and the GPS pmod. However, I am a little confused as to how the GPS pmod in the PL communicates with the Ubuntu on the ARM. I would really appreciate some insight on the last leg of this triangle of communication. For the bare-metal exercise, I used the IP blocks provided in the vivado-library. I noticed that there were a few files under the driver folder that were related to the software side, but I'm unsure how to move forward. When I rebuilt the Petalinux package with the hdf that included my GPS pmod, the module did not show up on Ubuntu. Do I need to create the hardware driver separate from the vivado-library files? If yes, is that using the petalinux tools or SDK or something different? I have already looked into most of the forum posts and Xilinx documentation provided for the Zedboard, pmods, and petalinux, but did not find an explicit explanation. Thank you in advance!
  2. Hi, I've opened the Cora-Z7-10-base-linux project in Vivado 2017.4 (to avoid any version-dependent issues) on Linux, and I was hoping to be able to route the UART 1 device from the ZYNQ7 Processing System out to the outside world. Ideally I'd like it to be wired up to the DP0 and DP1 pins, as I have a nice little Arduino Click2 adapter that I can put an RS485 Click board one. However, being very new to all this Zynq/Cora/Vivado stuff, I'm not sure how to do it. I started off (with a bit of advice from someone who knows more about this than me, but was rushing off home!) by opening the ZYNQ7 Processing System for re-customisation, and, in the Peripheral I/O Pins view, clicking on the EMIO button at the end of the UART1 row, and clicking OK. At this point, the block design is updated and UART_1 shows up on the ZYNQ7 Processing System block. Then I expanded UART_1 and, for each of the signals, right clicked and selected "Make external" before saving the block design and doing "Generate Block Design" again. The signal names related to UART 1 then showed up in the wrapper VHDL. Next, to try to map then to the Arduino I/O pins, I edited the constraints file by uncommenting and updating the ck_io0 and ck_io1 lines to be as follows: set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { UART1_RX_0 }]; #IO_L11P_T1_SRCC_34 Sch=ck_io[0] set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { UART1_TX_0 }]; #IO_L3N_T0_DQS_34 Sch=ck_io[1] Save, and "Generate Bitstream" to make all the steps run.. Unfortunately it breaks here with the following errors and critical warnings in the Messages view: Implementation Design Initialization [Vivado 12-1411] Cannot set LOC property of ports, Cannot set PACKAGE_PIN property of ports, port UART1_RX_0 can not be placed on PACKAGE_PIN U14 because the PACKAGE_PIN is occupied by port shield_dp0_dp13_tri_io[0] ["/home/jmccabe/work/Cora-Z7-10/Cora-Z7-10-base-linux/src/constraints/Cora-Z7-10-Master.xdc":92] Place Design [Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is greater than number of available sites (0). The following are banks with available pins: IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: In RangeId: 1 has only 0 sites available on device, but needs 1 sites. Term: UART1_RX_0 [Place 30-374] IO placer failed to find a solution Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | IO Placement : Bank Stats | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | Id | Pins | Terms | Standards | IDelayCtrls | VREF | VCCO | VR | DCI | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | 0 | 0 | 0 | | | | | | | | 13 | 0 | 0 | | | | | | | | 34 | 50 | 33 | LVCMOS33(33) | | | +3.30 | YES | | | 35 | 50 | 41 | LVCMOS33(41) | | | +3.30 | YES | | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | | 100 | 74 | | | | | | | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ IO Placement: +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | BankId | Terminal | Standard | Site | Pin | Attributes | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | 34 | Shield_I2C_scl_io | LVCMOS33 | IOB_X0Y1 | P16 | | | | Shield_I2C_sda_io | LVCMOS33 | IOB_X0Y2 | P15 | | | | Shield_SPI_io0_io | LVCMOS33 | IOB_X0Y29 | W15 | | | | Shield_SPI_io1_io | LVCMOS33 | IOB_X0Y46 | T12 | | | | d_dp0_dp13_tri_io[0] | LVCMOS33 | IOB_X0Y28 | U14 | | | | _dp0_dp13_tri_io[10] | LVCMOS33 | IOB_X0Y27 | U15 | | | | d_dp0_dp13_tri_io[1] | LVCMOS33 | IOB_X0Y43 | V13 | | | | d_dp0_dp13_tri_io[2] | LVCMOS33 | IOB_X0Y40 | T14 | | | | d_dp0_dp13_tri_io[3] | LVCMOS33 | IOB_X0Y39 | T15 | | | | d_dp0_dp13_tri_io[4] | LVCMOS33 | IOB_X0Y8 | V17 | | | | d_dp0_dp13_tri_io[5] | LVCMOS33 | IOB_X0Y7 | V18 | | | | d_dp0_dp13_tri_io[6] | LVCMOS33 | IOB_X0Y11 | R17 | * | | | d_dp0_dp13_tri_io[7] | LVCMOS33 | IOB_X0Y37 | R14 | * | | | d_dp0_dp13_tri_io[8] | LVCMOS33 | IOB_X0Y24 | N18 | | | | _dp26_dp41_tri_io[0] | LVCMOS33 | IOB_X0Y12 | R16 | | | | _dp26_dp41_tri_io[1] | LVCMOS33 | IOB_X0Y45 | U12 | | | | _dp26_dp41_tri_io[2] | LVCMOS33 | IOB_X0Y44 | U13 | | | | _dp26_dp41_tri_io[3] | LVCMOS33 | IOB_X0Y30 | V15 | | | | _dp26_dp41_tri_io[4] | LVCMOS33 | IOB_X0Y32 | T16 | | | | _dp26_dp41_tri_io[5] | LVCMOS33 | IOB_X0Y31 | U17 | | | | _dp26_dp41_tri_io[6] | LVCMOS33 | IOB_X0Y10 | T17 | | | | _dp26_dp41_tri_io[7] | LVCMOS33 | IOB_X0Y9 | R18 | | | | _dp26_dp41_tri_io[8] | LVCMOS33 | IOB_X0Y3 | P18 | | | | _dp26_dp41_tri_io[9] | LVCMOS33 | IOB_X0Y4 | N17 | | | | user_dio_tri_io[10] | LVCMOS33 | IOB_X0Y17 | W20 | | | | user_dio_tri_io[2] | LVCMOS33 | IOB_X0Y22 | N20 | | | | user_dio_tri_io[3] | LVCMOS33 | IOB_X0Y21 | P20 | | | | user_dio_tri_io[4] | LVCMOS33 | IOB_X0Y23 | P19 | | | | user_dio_tri_io[5] | LVCMOS33 | IOB_X0Y49 | R19 | | | | user_dio_tri_io[6] | LVCMOS33 | IOB_X0Y20 | T20 | | | | user_dio_tri_io[7] | LVCMOS33 | IOB_X0Y0 | T19 | | | | user_dio_tri_io[8] | LVCMOS33 | IOB_X0Y19 | U20 | | | | user_dio_tri_io[9] | LVCMOS33 | IOB_X0Y18 | V20 | | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | 35 | Shield_SPI_sck_io | LVCMOS33 | IOB_X0Y62 | H15 | | | | Shield_SPI_ss_io | LVCMOS33 | IOB_X0Y88 | F16 | | | | btns_2bits_tri_i[0] | LVCMOS33 | IOB_X0Y91 | D20 | | | | btns_2bits_tri_i[1] | LVCMOS33 | IOB_X0Y92 | D19 | | | | rgb_led[0] | LVCMOS33 | IOB_X0Y55 | L15 | | | | rgb_led[1] | LVCMOS33 | IOB_X0Y68 | G17 | | | | rgb_led[2] | LVCMOS33 | IOB_X0Y58 | N15 | | | | rgb_led[3] | LVCMOS33 | IOB_X0Y99 | G14 | | | | rgb_led[4] | LVCMOS33 | IOB_X0Y56 | L14 | | | | rgb_led[5] | LVCMOS33 | IOB_X0Y53 | M15 | | | | _dp0_dp13_tri_io[11] | LVCMOS33 | IOB_X0Y75 | K18 | | | | _dp0_dp13_tri_io[12] | LVCMOS33 | IOB_X0Y72 | J18 | | | | _dp0_dp13_tri_io[13] | LVCMOS33 | IOB_X0Y61 | G15 | * | | | d_dp0_dp13_tri_io[9] | LVCMOS33 | IOB_X0Y83 | M18 | | | | dp26_dp41_tri_io[10] | LVCMOS33 | IOB_X0Y84 | M17 | | | | dp26_dp41_tri_io[11] | LVCMOS33 | IOB_X0Y77 | L17 | | | | dp26_dp41_tri_io[12] | LVCMOS33 | IOB_X0Y73 | H17 | | | | dp26_dp41_tri_io[13] | LVCMOS33 | IOB_X0Y71 | H18 | | | | dp26_dp41_tri_io[14] | LVCMOS33 | IOB_X0Y67 | G18 | | | | dp26_dp41_tri_io[15] | LVCMOS33 | IOB_X0Y81 | L20 | | | | user_dio_tri_io[0] | LVCMOS33 | IOB_X0Y82 | L19 | | | | user_dio_tri_io[11] | LVCMOS33 | IOB_X0Y80 | K19 | | | | user_dio_tri_io[1] | LVCMOS33 | IOB_X0Y86 | M19 | | | | vaux0_v_n | LVCMOS33 | IOB_X0Y97 | B20 | | | | vaux0_v_p | LVCMOS33 | IOB_X0Y98 | C20 | | | | vaux12_v_n | LVCMOS33 | IOB_X0Y69 | F20 | | | | vaux12_v_p | LVCMOS33 | IOB_X0Y70 | F19 | | | | vaux13_v_n | LVCMOS33 | IOB_X0Y63 | G20 | | | | vaux13_v_p | LVCMOS33 | IOB_X0Y64 | G19 | | | | vaux15_v_n | LVCMOS33 | IOB_X0Y51 | J16 | | | | vaux15_v_p | LVCMOS33 | IOB_X0Y52 | K16 | | | | vaux1_v_n | LVCMOS33 | IOB_X0Y93 | D18 | | | | vaux1_v_p | LVCMOS33 | IOB_X0Y94 | E17 | | | | vaux5_v_n | LVCMOS33 | IOB_X0Y65 | H20 | | | | vaux5_v_p | LVCMOS33 | IOB_X0Y66 | J20 | | | | vaux6_v_n | LVCMOS33 | IOB_X0Y59 | J14 | | | | vaux6_v_p | LVCMOS33 | IOB_X0Y60 | K14 | | | | vaux8_v_n | LVCMOS33 | IOB_X0Y95 | A20 | | | | vaux8_v_p | LVCMOS33 | IOB_X0Y96 | B19 | | | | vaux9_v_n | LVCMOS33 | IOB_X0Y89 | E19 | | | | vaux9_v_p | LVCMOS33 | IOB_X0Y90 | E18 | | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ [Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. [Common 17-69] Command failed: Placer could not place all instances It seems that I naively thought that those lines being commented out meant those signals weren't connected (shows how little I know!). Can anyone give me any pointers on how to overcome this, or how I should be doing this? Any help will be very gratefully appreciated. John
  3. Hello everyone! I'm trying to install Petalinux on a Cora Z7-10 I followed all the steps described here: github.com/Digilent/Petalinux-Cora-Z7-10 but when I try to boot it I get this message: hwclock: can't open '/dev/misc/rtc': no such file or directory after this, I can't write anything in Minicom. As in my folder /dev didn't have the misc folder, following some advice that I found on the net I created the folder and first tried to soft-link /dev/rtc0 and then hard-link it also but none of those worked, I still get the same error. Did anyone go through the same issue or has any idea to solve it? Thanks you very much in advance.
  4. Can someone guide me how to get Petalinux working on Zybo Z7-20? I am using Vivado and SDK 2018.3 on Windows 10. I prefer using prebuilt images and files if they are available. I found this link, but it seems it is very old, and I am not sure if I can use it on my version of Vivado and SDK: https://github.com/Digilent/Petalinux-Zybo-Z7-20 The Xilinx links for Petalinux are available here: https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-design-tools.html If there exists any other easy method for installing any type of Linux please help me.
  5. Hi Everyone, I'm new to Zynq FPGA and I have some difficulties to understand how to program the PL through Petalinux. I have a Cora Z7-07S board and by fallowing Digilent's instruction (https://reference.digilentinc.com/reference/software/petalinux/start), I'm able to boot Petalinux on a SDcard and SSH to it. I can also load the basic PL demo (https://reference.digilentinc.com/reference/programmable-logic/cora-z7/cora-z7-07s-basic-io) through the JTAG with Vivado. But I'm struggling trying to program the PL with the same demo program trough Petalinux. If I understand correctly this guide: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841645/Solution+Zynq+PL+Programming+With+FPGA+Manager, I have to change the device-tree to add the top.bit.bin. Does anyone know which files of Digilent's BSP should be changed and how? Can anyone provide a step by step guide? Thank you
  6. Hello, I've been to set up a new Zybo board but I'm stuck with a serial port issue. I built my design with the provided board files in Vivado 2017.4. I tried a simple "hello world" in SDK but only got a bunch of unprintable characters. I have Tera Term set up for 115200, 8-bit, 1 stop, no parity. I tried Putty as well and had the same results. I verified the Vivado project is using UART1 MIO48..49. I intermittently can get the correct initialization message from the preloaded QSPI image, but most times it's unprintable characters. I also tried the pre-built Linux from the 2017.4 Zybo Petalinux BSP with the same result. It's definitely booting, but the terminal output is unprintable characters. Other things to note: * I'm running off USB power. I'm plugged directly into my laptop * Sometimes pressing the Reset button makes the PGOOD LED flicker until power cycled Thank you Richard
  7. I created a petalinux project using the following commands and wanted to use my own Hardware Description File (.hdf) generated by IP Integration Demo. I have attached the Hardware Description files exported by vivado 2016.4. $petalinux-create --type project -s ./Petalinux-Zybo-Z7-20-2017.4-2.bsp --name hf2-petalinux $cd hf2-petalinux $petalinux-config --get-hw-description=/home/jeremy/workspace/vivadoProj/IpIntegrate/IpIntegrate.sdk/IpI_wrapper_hw_platform_0/ But I cann't build the petalinux project to generate images when I stepped to run `petalinux-build` command. The info prompted to the terminal is as follows: jeremy@j-XPS-8700:~/workspace/zybo-z7-20/hf2-petalinux$ petalinux-build --verbose [INFO] building project [INFO] sourcing bitbake INFO: bitbake petalinux-user-image Loading cache: 100% |#####################################################################| Time: 0:00:00 Loaded 3257 entries from dependency cache. Parsing recipes: 100% |###################################################################| Time: 0:00:01 Parsing of 2473 .bb files complete (2434 cached, 39 parsed). 3266 targets, 226 skipped, 0 masked, 0 errors. NOTE: Resolving any missing task queue dependencies Initialising tasks: 100% |################################################################| Time: 0:00:05 Checking sstate mirror object availability: 100% |########################################| Time: 0:00:01 NOTE: Executing SetScene Tasks NOTE: Executing RunQueue Tasks fsbl-2017.4+gitAUTOINC+77448ae629-r0 do_compile: NOTE: fsbl: compiling from external source tree /opt/pkg/petalinux/tools/hsm/data/embeddedsw ERROR: device-tree-generation-xilinx+gitAUTOINC+3c7407f6f8-r0 do_compile: Function failed: do_compile (log file is located at /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/temp/log.do_compile.14317) ERROR: Logfile of failure stored in: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/temp/log.do_compile.14317 Log data follows: | DEBUG: Executing shell function do_compile | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:77.1-14 Label or path axi_dynclk_0 not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:82.1-12 Label or path axi_vdma_1 not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:85.1-10 Label or path v_tc_out not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:91.1-9 Label or path v_tc_in not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:94.1-12 Label or path axi_vdma_0 not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:97.1-16 Label or path axi_gpio_video not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:100.1-9 Label or path pwm_rgb not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:139.1-15 Label or path axi_i2s_adi_0 not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:155.1-14 Label or path axi_gpio_led not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:160.1-17 Label or path axi_gpio_sw_btn not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:164.1-14 Label or path axi_gpio_eth not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:201.1-11 Label or path axi_iic_0 not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:225.1-26 Label or path mipi_csi2_rx_subsystem_0 not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:264.1-15 Label or path v_frmbuf_wr_0 not found | FATAL ERROR: Syntax error parsing input tree | WARNING: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/temp/run.do_compile.14317:1 exit 1 from 'dtc -I dts -O dtb -R 8 -p 0x1000 -i /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0 -i /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/../components/plnx_workspace/device-tree/device-tree-generation -o /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/../components/plnx_workspace/device-tree/device-tree-generation/plnx_arm-system.dtb /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/../components/plnx_workspace/device-tree/device-tree-generation/plnx_arm-system.pp' | ERROR: Function failed: do_compile (log file is located at /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/temp/log.do_compile.14317) ERROR: Task (/opt/pkg/petalinux/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree-generation_git.bb:do_compile) failed with exit code '1' NOTE: Tasks Summary: Attempted 3295 tasks of which 3288 didn't need to be rerun and 1 failed. Summary: 1 task failed: /opt/pkg/petalinux/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree-generation_git.bb:do_compile Summary: There was 1 ERROR message shown, returning a non-zero exit code. ERROR: Failed to build project webtalk failed:PetaLinux statistics:extra lines detected:notsent_nofile! webtalk failed:Failed to get PetaLinux usage statistics! Does anyone have any work-around to the errors? Any points would be appreciated! PS: I have separately tested the application of IP Integration Demo to bare-metal (Zybo-z7-20) and petalinux project using default Hardware Description configuration. Kept all default options when running `petalinux-config -c u-boot`, `petalinux-config -c kernel`, and `petalinux-config -c rootfs`. Additionally, I have tried to split `petalinux-build` process by several detailed steps, i.e., running `petalinux-build -c bootloader`, `petalinux-build -c u-boot` and other following commands. The first one `petalinux-build -c bootloader` can be finished successfully. But when I execute `petalinux-build -c u-boot`, the errors similar to above prompt out. IpI_wrapper_hw_platform_0.tar.gz
  8. Hi, I came across this tutorial that @Commanderfranz created for the Zybo https://www.instructables.com/id/Embedded-Linux-Tutorial-Zybo/. It is also referenced here: https://blog.digilentinc.com/zybo-embedded-linux-hands-on-tutorial/, which also includes the "Embedded Linux Tutorial for the Zedboard". As far as I can tell the Embedded Linux Tutorial for the Zedboard uses the Xilinx ISE instead of Vivado. What differences will there be to follow the "Embedded Linux Tutorial for the Zedboard" tutorial in Vivado? Likewise, what differences will I have to make if I follow the https://www.instructables.com/id/Embedded-Linux-Tutorial-Zybo/ on the Zedboard? My initial skimming of the tutorial makes me think that the most obvious thing will be changing the constraints to match the Zedboard for the custom LED IP that is being created. The only other thing that I see that would need to be changed is creating the base system. The base Zybo system looks like a simple Zynq IP with a few GPIO modules to support the LEDS, switches and buttons. Is there anything else that I would need to include for it? Or perhaps is there a better/bigger image of what the Zybo base system looks like? Thanks, Stuart
  9. Hello everyone, I've bought a Zybo Z7 with a XC7Z010. I've downloaded the HDMI demo (link here) and I got it working - I connected my laptop to the RX port and a monitor to the TX port. Now what I'm trying to do is to have the TX connected to a monitor, build an image using Petalinux and once I program the SoC I can see the Linux booting on the monitor. I've built an image using the bit and hdf files provided on the HDMI demo project and on Petalinux kernel config I've enabled the following: Device Drivers -> Graphics support -> Enable HDMI HDCP support in MSM DRM driver -> Xilinx DRM -> Xilinx DRM Display Port Driver -> Xilinx DRM Display Port Subsystem Driver I can program the SoC ok but I get no output on the monitor. Am I missing something? Thanks in advance!
  10. Hello, everyone. I am new here in this form and also with zybo. I have been working on one zybo project. I am finished with vivado design. but now I am working with the petalinux tool to create bootable sd card. I have read the tutorial to create a bootable image for Debian Jessie (it can boot perfectly). but I could not find proper materials to modify my devicetree file in order to work with VGA and other peripherals to make complete pc. can you please suggest me proper tutorials or articles? thank you
  11. Hi, I am trying to create and install an application for Zynq using PetaLinux. I have created a new project as per ug980 and have created an app as per ug981. When I run 'petalinux-build -c rootfs/myapp' it fails with ERROR: Nothing PROVIDES 'rootfs/myapp'. I have not edited the source code. I am just trying to build myapp into the existing system image. Another observation is, when I built gpio-demo. It threw ERROR: Nothing PROVIDES 'rootfs/gpio-demo'. Close matches: gpio-demo. I am wondering what would have caused the error.
  12. Hello, I am using Zed board 7000. I want to do Image Processing or basic computation in Zed board on PL side using FPGA. I was a bit confused to start either with a Linux image(PetaLinux or Xillinux) or directly through the Vivado software. Is it possible to do any computation or Image Processing on the PL side using ARM processor only to interface the peripherals(I don't want the computation to be done on the ARM processor). Kindly provide any reference link or tutorial which can address my queries. Thanks in advance. ---Nikith--
  13. Nikith

    Petalinux or Xillinux

    Hi, Which one is better Petalinux or Xillinux? If yes, Why? Thanks in advance. --Nikith--
  14. Hello! Here is another newbie question from me! I am having a running hardware project from Vivado, and I also debugged bare metal code with SDK. Both was running perfectly. Now I also got a PetaLinux (v2017.4) run on my Zybo Z7-20. So far so good. First I thought, that I could only paste the c code on PetaLinux, compile it and let it run. But of course it didn't worked because I used bare metal code. I wrote already that I have to add drivers to the device tree. Here are my problems/questions: 1) I wrote something the following files: system-user.dtsi, zynq-7000.dtsi, system-top.dts and system-conf.dtsi As I wrote I am only allowed to change stuff in the system-user.dtsi file. But when I compare the driver code from your Zybo Z7-20 and the stuff I found in the internet. It looks completly different. So where and what do I have add? I wrote that I have to enable the kernel configuration (where and how)? Am I doing this with petalinux-config -c kernel, is it also possible that when I use my own hardwaretarget for PetaLinux creating , that the enabeling of the drivers happened already? 2) I want to send the voltage values over ethernet, so do I need one or two drivers (XADC-driver or XADC + ethernet-driver) for it and also a gpio driver, right? Is there code for Zybo Z7-20 somewhere existing, or where can I find some code that is fitting? I made more trys but never the petalinux-build was successfully. Thanks again for your help and time, it is always totally helpful! A+ for your job, helping a totally newbie ;-) greetings,
  15. Hello, I have a question about audio. I've already asked about the issue. Another question is "Known Issues" of the BSP provided in "github". (https://github.com/Digilent/Petalinux-Zybo-Z7-10/blob/v2017.2-1/README.md) What does "Audio is currently completely non-functional" mean in "Known Issues"? Does "Zybo Z7-10" mean it is impossible to run audio properly? Do you provide a BSP that solves this problem? We did not have to buy the "Zybo Z7-10" if Audio was not supported. I would appreciate your help in more depth. Regards, Namio
  16. Dear Experts I am currently using Petalinux 2015.4 on Zedboard. I have connected a Transcend CF Card through USB 2250 Evaluation Board through USB-OTG. Now the issue I am facing right now is I can't hot swap CF cards, i.e. if I plug out the CF card from EVB and plug it in, the linux doesnot enumerates it until Zedboard is restarted. Kindly help me in this issue. P.S. I got USB-OTG working by adding following lines to system-top.dts: /dts-v1/; /include/ "system-conf.dtsi" /{ usb_phy0:phy0 { compatible="ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port=<0x170>; drv-vbus; }; }; &usb0 { status = "okay"; dr_mode = "host"; usb-phy = <&usb_phy0>; } ; Regards
  17. Hi, I have been following the instruction on https://github.com/Digilent/Petalinux-Arty-Z7-20. These are well done and I got a running image on a SD card from the cloned git repo. Then I switched to the Digilent Apps description, changed some config and recreated the image. This one stopped after the message "Starting kernel..." After some tries, it turned out that just rebuilding the image even without any change leads to that behaviour. However, cleaning the build will again give a correct image. But I believe thats not the intention to clean for each build... What do I miss? Thanks for your help, Juergen
  18. Hello, i wish to expand my Basic Linux image (petalinux) with the apt-get package. Therefor i used the "petalinux-config -c rootfs" command. But i do not find the right package for the "apt-get"-tool. My Primary issue is to install the libgcc because the Xilinx SDK told me, that i Need that library to run my c-code. - How do i install the apt-get package (where to find)? - How do i install a so called "gcclib_s.so.1" or something like that? Thank you...
  19. Hello, finally i was able to make a petalinux build with the BSP 2017.4 - so far, so good. Then i find out, which uio device is connected with the Arty-Z7-20 Buttons and switches. Both - the Buttons and also the Switches - are connected to one GPIO-IP-Core (Dual-Channel, all inputs). One AXI-GPIO has one base address and a dual channel GPIO has even only one base address. So the only way to address both channels is to use the base address offset for channel one and for channel two, isn't it? If i read channel one - which is assigned to the Buttons - then i can read the Buttons. If i read the channel two (Switches) - one code line later - then i got no result. So my questions is: What must i do to read the Arty-Z7-20 Switches (petalinux, BSP 2017.4)? Thank you...
  20. Hello, i made the following design: You can see two GPIO Ports: - GPIO_RGB_LED, 3 Bit, Output only - GPIO_SW, two data bits plus one interrupt bit (e.g. Input clk), this port should throw Interrupts into the Linux App. After i build that design with Vivado, i used petalinux to create a Linux image. Here you can see the "/dev"-Folder which contains the installed Drivers: You can see three GPIO-Drivers. Now my question: In former questions i ask for the Driver Support in Linux and how i can write or use them. You told me, that there is a simple way to access memory mapped ip-cores with the "uio"-Driver. First i was glad to see that the Drivers are automaticaly added to the image. But i'am missing the expected "uio"-Drivers. What must i do to get the "uio"-Drivers for my design with petalinux? Thank you...
  21. Hey evryone ! i am using zybo 7010 in ubunto 16.04 I generate a BOOT.BIN and an image.ub, I put the two files in the SD card but it does not boot! in vivado i activate UART0 and UART1. jumper is good. I enclose the two files system-user.dtsi and system-conf.dtsi. my serial terminal is /dev/ttyUSB1. please helpe ! system-user.dtsi system-conf.dtsi
  22. I'm trying to build the Arty-Z7-20 petalinux project version 2017.4 but it keeps failing because off: libuio-1.0-r0 do_fetch libgpio-1.0-r0 do_fetch libpwm-1.0-r0 do_fetch gpiotil-1.0-r0 do_fetch pwmdemo-1.0-r0 do_fetch failing, because the connection times out, is there a way to bypass this?
  23. Hello, i have some errors while building the 2017.4 BSP based petalinux image. czymic@ubuntu:~/projects/2017.4/Arty-Z7-20$ petalinux-build [INFO] building project [INFO] sourcing bitbake INFO: bitbake petalinux-user-image Parsing recipes: 100% |##########################################| Time: 0:01:30 Parsing of 2473 .bb files complete (0 cached, 2473 parsed). 3266 targets, 226 skipped, 0 masked, 0 errors. NOTE: Resolving any missing task queue dependencies Initialising tasks: 100% |#######################################| Time: 0:00:06 Checking sstate mirror object availability: 100% |###############| Time: 0:00:18 NOTE: Executing SetScene Tasks NOTE: Executing RunQueue Tasks ERROR: libuio-1.0-r0 do_fetch: Fetcher failure: Fetch command export DBUS_SESSION_BUS_ADDRESS="unix:abstract=/tmp/dbus-lkhXXEii1h"; export SSH_AUTH_SOCK="/run/user/1000/keyring/ssh"; export GIT_SSL_CAINFO="/home/czymic/petalinux/2017.4/components/yocto/source/arm/buildtools/sysroots/x86_64-petalinux-linux/etc/ssl/certs/ca-certificates.crt"; export PATH="/home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/sysroots-uninative/x86_64-linux/usr/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/layers/core/scripts:/home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/sysroots/x86_64-linux/usr/bin/arm-xilinx-linux-gnueabi:/home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/sysroots/plnx_arm/usr/bin/crossscripts:/home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/sysroots/x86_64-linux/usr/sbin:/home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/sysroots/x86_64-linux/usr/bin:/home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/sysroots/x86_64-linux/sbin:/home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/sysroots/x86_64-linux/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/layers/core/scripts:/home/czymic/petalinux/2017.4/components/yocto/source/arm/layers/core/bitbake/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/sysroots/x86_64-petalinux-linux/usr/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/buildtools/sysroots/x86_64-petalinux-linux/usr/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/usr/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/usr/sbin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/sbin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/usr/bin/../x86_64-petalinux-linux/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/usr/bin/arm-xilinx-linux-gnueabi:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/usr/bin/arm-xilinx-linux-uclibc:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/usr/bin/arm-xilinx-linux-musl:/home/czymic/petalinux/2017.4/tools/common/petalinux/utils:/home/czymic/petalinux/2017.4/tools/linux-i386/petalinux/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/petalinux/bin/unexport:/home/czymic/petalinux/2017.4/tools/hsm/bin:/home/czymic/petalinux/2017.4/tools/webtalk/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/petalinux/bin:/home/czymic/petalinux/2017.4/tools/common/petalinux/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/gcc-arm-none-eabi-r5/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/microblaze-xilinx-elf/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/microblazeel-xilinx-linux-gnu/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/gcc-arm-none-eabi/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/gcc-arm-linux-gnueabi/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/aarch64-none-elf/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/aarch64-linux-gnu/bin:/home/czymic/bin:/home/czymic/.local/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin"; export HOME="/home/czymic"; git -c core.fsyncobjectfiles=0 ls-remote git://github.com/mitchellorsucci/libuio.git failed with exit code 128, output: fatal: unable to connect to github.com: github.com[0: 192.30.253.112]: errno=Connection refused github.com[1: 192.30.253.113]: errno=Connection refused ERROR: libuio-1.0-r0 do_fetch: Function failed: base_do_fetch ERROR: Logfile of failure stored in: /home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/libuio/1.0-r0/temp/log.do_fetch.48850 ERROR: Task (/home/czymic/projects/2017.4/Arty-Z7-20/project-spec/meta-user/recipes-apps/digilent-apps/libuio/libuio.bb:do_fetch) failed with exit code '1' ERROR: libgpio-1.0-r0 do_fetch: Fetcher failure: Fetch command export DBUS_SESSION_BUS_ADDRESS="unix:abstract=/tmp/dbus-lkhXXEii1h"; export SSH_AUTH_SOCK="/run/user/1000/keyring/ssh"; export GIT_SSL_CAINFO="/home/czymic/petalinux/2017.4/components/yocto/source/arm/buildtools/sysroots/x86_64-petalinux-linux/etc/ssl/certs/ca-certificates.crt"; export PATH="/home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/sysroots-uninative/x86_64-linux/usr/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/layers/core/scripts:/home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/sysroots/x86_64-linux/usr/bin/arm-xilinx-linux-gnueabi:/home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/sysroots/plnx_arm/usr/bin/crossscripts:/home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/sysroots/x86_64-linux/usr/sbin:/home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/sysroots/x86_64-linux/usr/bin:/home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/sysroots/x86_64-linux/sbin:/home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/sysroots/x86_64-linux/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/layers/core/scripts:/home/czymic/petalinux/2017.4/components/yocto/source/arm/layers/core/bitbake/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/sysroots/x86_64-petalinux-linux/usr/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/buildtools/sysroots/x86_64-petalinux-linux/usr/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/usr/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/usr/sbin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/sbin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/usr/bin/../x86_64-petalinux-linux/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/usr/bin/arm-xilinx-linux-gnueabi:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/usr/bin/arm-xilinx-linux-uclibc:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/usr/bin/arm-xilinx-linux-musl:/home/czymic/petalinux/2017.4/tools/common/petalinux/utils:/home/czymic/petalinux/2017.4/tools/linux-i386/petalinux/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/petalinux/bin/unexport:/home/czymic/petalinux/2017.4/tools/hsm/bin:/home/czymic/petalinux/2017.4/tools/webtalk/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/petalinux/bin:/home/czymic/petalinux/2017.4/tools/common/petalinux/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/gcc-arm-none-eabi-r5/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/microblaze-xilinx-elf/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/microblazeel-xilinx-linux-gnu/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/gcc-arm-none-eabi/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/gcc-arm-linux-gnueabi/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/aarch64-none-elf/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/aarch64-linux-gnu/bin:/home/czymic/bin:/home/czymic/.local/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin"; export HOME="/home/czymic"; git -c core.fsyncobjectfiles=0 ls-remote git://github.com/mitchellorsucci/libgpio.git failed with exit code 128, output: fatal: unable to connect to github.com: github.com[0: 192.30.253.113]: errno=Connection refused github.com[1: 192.30.253.112]: errno=Connection refused ERROR: libgpio-1.0-r0 do_fetch: Function failed: base_do_fetch ERROR: Logfile of failure stored in: /home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/libgpio/1.0-r0/temp/log.do_fetch.48851 ERROR: Task (/home/czymic/projects/2017.4/Arty-Z7-20/project-spec/meta-user/recipes-apps/digilent-apps/libgpio/libgpio.bb:do_fetch) failed with exit code '1' ERROR: libpwm-1.0-r0 do_fetch: Fetcher failure: Fetch command export DBUS_SESSION_BUS_ADDRESS="unix:abstract=/tmp/dbus-lkhXXEii1h"; export SSH_AUTH_SOCK="/run/user/1000/keyring/ssh"; export GIT_SSL_CAINFO="/home/czymic/petalinux/2017.4/components/yocto/source/arm/buildtools/sysroots/x86_64-petalinux-linux/etc/ssl/certs/ca-certificates.crt"; export PATH="/home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/sysroots-uninative/x86_64-linux/usr/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/layers/core/scripts:/home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/sysroots/x86_64-linux/usr/bin/arm-xilinx-linux-gnueabi:/home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/sysroots/plnx_arm/usr/bin/crossscripts:/home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/sysroots/x86_64-linux/usr/sbin:/home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/sysroots/x86_64-linux/usr/bin:/home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/sysroots/x86_64-linux/sbin:/home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/sysroots/x86_64-linux/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/layers/core/scripts:/home/czymic/petalinux/2017.4/components/yocto/source/arm/layers/core/bitbake/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/sysroots/x86_64-petalinux-linux/usr/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/buildtools/sysroots/x86_64-petalinux-linux/usr/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/usr/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/usr/sbin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/sbin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/usr/bin/../x86_64-petalinux-linux/bin:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/usr/bin/arm-xilinx-linux-gnueabi:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/usr/bin/arm-xilinx-linux-uclibc:/home/czymic/petalinux/2017.4/components/yocto/source/arm/tmp/sysroots/x86_64-linux/usr/bin/arm-xilinx-linux-musl:/home/czymic/petalinux/2017.4/tools/common/petalinux/utils:/home/czymic/petalinux/2017.4/tools/linux-i386/petalinux/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/petalinux/bin/unexport:/home/czymic/petalinux/2017.4/tools/hsm/bin:/home/czymic/petalinux/2017.4/tools/webtalk/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/petalinux/bin:/home/czymic/petalinux/2017.4/tools/common/petalinux/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/gcc-arm-none-eabi-r5/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/microblaze-xilinx-elf/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/microblazeel-xilinx-linux-gnu/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/gcc-arm-none-eabi/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/gcc-arm-linux-gnueabi/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/aarch64-none-elf/bin:/home/czymic/petalinux/2017.4/tools/linux-i386/aarch64-linux-gnu/bin:/home/czymic/bin:/home/czymic/.local/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin"; export HOME="/home/czymic"; git -c core.fsyncobjectfiles=0 ls-remote git://github.com/mitchellorsucci/libpwm.git failed with exit code 128, output: fatal: unable to connect to github.com: github.com[0: 192.30.253.112]: errno=Connection refused github.com[1: 192.30.253.113]: errno=Connection refused ERROR: libpwm-1.0-r0 do_fetch: Function failed: base_do_fetch ERROR: Logfile of failure stored in: /home/czymic/projects/2017.4/Arty-Z7-20/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/libpwm/1.0-r0/temp/log.do_fetch.52387 ERROR: Task (/home/czymic/projects/2017.4/Arty-Z7-20/project-spec/meta-user/recipes-apps/digilent-apps/libpwm/libpwm.bb:do_fetch) failed with exit code '1' NOTE: Tasks Summary: Attempted 1534 tasks of which 1513 didn't need to be rerun and 3 failed. Summary: 3 tasks failed: /home/czymic/projects/2017.4/Arty-Z7-20/project-spec/meta-user/recipes-apps/digilent-apps/libuio/libuio.bb:do_fetch /home/czymic/projects/2017.4/Arty-Z7-20/project-spec/meta-user/recipes-apps/digilent-apps/libgpio/libgpio.bb:do_fetch /home/czymic/projects/2017.4/Arty-Z7-20/project-spec/meta-user/recipes-apps/digilent-apps/libpwm/libpwm.bb:do_fetch Summary: There were 6 ERROR messages shown, returning a non-zero exit code. ERROR: Failed to build project ==================================================================================================================================================== What must i do, to be able to build the BSP based image with: petalinux-create -t project -s <Path to BSP> and petalinux-build Thank you...
  24. Hello, i have a new created petalinux project for the zynq processor (Arty-Z7-20). I'am not using a digilent bsp file to configure the project, because i have a simple selfmade design and i like to start with a minimalistic Linux. I like to support Linux pthread and sockets, thats all. If i implement a tcp/ip Server and if i use the select Routine to wait for incomming data then the "select" Routine does not return, even if i receive data. In an other thread here in this Forum i discuss a similar issue. There i have a Problem with the "uio" Interrupt handling, because the blocking read does not return. So i think, that these two different issues have the same reason. My Linux image is not able to generate Events which can Trigger the "select" Statement. How can i enable the petalinux ability to handle "select"-commands? Thank you...
  25. deppenkaiser

    Zedboard

    Hello, i have an other question: If i look in the Mouser electronic shop i see, that the zedboard is associated with digilent and you Show on https://store.digilentinc.com/zedboard-zynq-7000-arm-fpga-soc-development-board/ the board. Why do you have no support on https://reference.digilentinc.com/reference/software/petalinux/start for the zedboard? Thank you...