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Found 59 results

  1. Hello, I've been strugling with de micro-sd card in Nexys-4 for quite some time. I'm using the code at sd_spi.vhd by Lawrence Wilkinson, but the FPGA never gets a valid answer from the card so it keeps looping forever (CMD8) I think I've checked all the obvious things : - Trying an old card, just in case SDHC was not properly suported - Booting the FPGA from the SD card (not USB), to check that the physical circuits were working properly - Trying with 3 different Nexys 4 boards - Lowering clock frequency to only a few hertzs (normal speed should be 50MHz, and a counter insides L.W. code slows it down for start-up) - Making sure that all jumper settings were put to SD So it's time to ask if someone has tryed to do the same with this board. I just need a simple way to read data from the SD card. I don't need a file system and using an embedded processor is too much hassle. If anybody wants to give it a try, the code is here: Project code (Constraints only for Vivado) Also, to avoid you the burden of downloading it, these are the pins I've being using (just in case is something that embarrasing obvious as using the wrong pin): set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; Thanks in advance Roberto
  2. Hi, I want to use Nexys4 ddr board to read sdcard, reference this topic and read @jpeyron answer, but after I create the block design with Pmod_SDcard ip and generate bitstream and launch Vivado18.2 SDK tool, an error for new Application Project occur, it may relate to this PmodSD IP, but I an new for using SDK tools. Can you help me how to deal with this error? Thank you! design_1_wrapper.hdf
  3. Hi I am new to microblaze. I have to design an efficient ALU using microblaze in Nexys 4 Anyone can guide through me the procedure ( I know the general guide line) and refer any document to do it Regards Uzmeed
  4. Hello everyone I want to know if there is a board description file for the Nexys4 that i can use with Xilinx System Generator ? I know that Digilent already made a board description file in order to use the Nexys4 with Vivado. Thank you
  5. Junior_jessy

    Voice-activited

    Hello, I'm trying to make a voice-activated on a nesys4 and i want to use the pmodMic3.To do si, I want to use the SPI protocol but i don't know how. So how can i choose the SPI protocol ? Furthermore, I got some issues when filling in the constraint's file. On the web-site of Diligent, the pin2 is not connected but, the protocol SPI show the opposite. So how to Well connect the in/out of the peripheral to the board in the constraint's file? Thank you in advance for your answer. Junior
  6. Hi. I use nexys4 with vivado for do partial reconfiguration. After several test the open hardware manager lost comunication with nexys4. I can load simple .bit files and files of partial reconfiguration using PlanAhead, but I can not down again files using vivado. The same happened with 2 board nexys4. ┬┐What can I do?
  7. elevator program is not working on the board and it is showing simulation properly.i am not getting where the mistake is happend.can you check the program why it is not working on the board.i thought that the mistake is in the elevator module.it is not taking any inputs according to the module. thanks elevator12.txt
  8. 5v dc motor is not rotating when I connect to pmod ja0 and it is working fine when I connected to vcc and gnd in the pmod ja. anyone can help me .. ???
  9. How to connect the pins in the nexys4 artix7 temperature sensor
  10. Hello, After downloading the project code found here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-keyboard-demo/start and programming my Nexys4 DDR, I can not get my board to read keyboard inputs. I've tried three different USB keyboards (Apple, Razor, and Logitech). To make sure that there was nothing wrong with the USB port, I performed the selftest as specified in the manual: "Connecting a mouse to the USB-HID Mouse port will allow the pointer on the VGA display to be controlled. Only mice compatible with the Boot Mouse HID interface are supported." One of the mice I tested allowed me to move the pointer on the VGA display. This leads me to believe that the USB port on my board is working. So I have three questions moving forward: Do I need a specific jumper configuration to read keyboard input? Does anyone know of a make/model of keyboard which is guaranteed to work with the board? Are there any self tests to show that keyboard input is indeed being received? I found this in the manual under section 3.3 of the reference manual: "For example, if a USB keyboard is plugged in, a rapid blink will signal the receipt of an HID input report from the keyboard." However, its placement in the manual leaves me uncertain that it is in fact a built in self test. That is, I am unsure if a keyboard plugged in during the demo configuration will make the "busy" light blink rapidly. Thank you.
  11. Hello Is it possible to program NEXYS 4 DDR with Xilinx ISE 14.7 Thank you in advance
  12. Hi, I just brought the NEXYS 4 FPGA and want to start learn it myself. The first project I am trying to do is changing the seven segment display one by one. Is there any example code that I can start with? Thank you.
  13. Hello, I have a code that interface keyboard to display scan code. I have wireless keyboard that doesn't respond when I press key, while wire or old style keyboard work just fine. the keyboard model is logitech k400r
  14. Hi, I just installed vivado 2017.2 on my PC, running windows 7 Service Pack1 (64-bit). I connected my Nexys 4 board using the cable that comes with the board in the package. When I attempted to connect the board to my PC, by clicking Open Hardware Manager -> Open Target -> Auto Connect, in the Hardware window in vivado, it shows localhost(0), which means no device detected. I also get 2 warnings below: warning: cannot open library dpcomm.dll, first required symbol ftdimgr_lock, Digilent FTDI based JTAG cables cannot be supported warning: cannot open library djtg.dll, first required symbol DjtgGetPortCount, select Digilent JTAG cables cannot be supported I noticed a post in a non-English Digilent forum, in which someone else was experiencing the exact same issue. Please help. yy
  15. Hello digilent support team, i have got a problem with my nexys 4 board. After i connected the board to a external power supply of 5V the board is death. I connected the positive pol of the source with the positive pol of the sink and the negative pol with GND of the board. I found the schematic of the nexys 4 board and made some measurement on my death board. I measure 5V at PIN 12/13 of IC22 ADP2118 but i don't measure 3.3V at PIN 6 at IC18 ADM1086, in the schematic the name of this voltage is FT3V3. But I coundn't find the source of FT3V3 in the schematic. Can you give me the name of the IC which produces the voltage FT3V3 or the part of the schematic? I disassambled IC18 and connected PIN 15 of IC22 with VU5V0. Now the supply voltages VCC1V8, VCC3V3 and VCC1V0 are fine and LD22 is red but i don't get i connection to the board with Vivado. What's wrong with the board...?? Have a nice day... Greatings from germany
  16. I'm writing a cpu on Nexys 4 DDR, but I have a problem: The DDR2 memory on Nexys4 will be reset whenever a new .bit file is written to the FPGA. I have already generated two .bit files. One is to write instructions and data to the DDR2 memory, and the other is the cpu program. What should I do to make the DDR2 memory remain the same even after it's programmed? Thank you!
  17. Hi I am trying to send data from Nexys 4 Artix 7 FPGA Board to PC. I using uart to send the data at 9600 baud rate. The uart takes data through the switch and I am using SW(0 to 7) for this. The data transfer takes place only when button is press(btnU). I wanted to make this transfer automatic without having the need to use the button but have not been able to get it done. I have taken the code from http://www.instructables.com/id/UART-Communication-on-Basys-3-FPGA-Dev-Board-Power/?ALLSTEPS. I have made some change to replace the btnU with "State" to initiate the the data transfer. For this purpose i have written a module where the input State determines whether to initiate the uart just like the btnU. The modules transmit and transmitter are sub-modules to the XADC module. Please find my code below: module transmit ( input clk, //clock signal input State, output reg transmit //transmit signal ); always @(posedge clk) begin if (State == 1) transmit <= 1; else transmit <= 0; end endmodule ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- module transmitter( input clk, input transmit, input [7:0] data, output reg TxD ); //internal variables reg [3:0] bitcounter; reg [13:0] counter; reg state,nextstate; reg [9:0] rightshiftreg; reg shift; reg load; reg clear; //UART transmission logic always @ (posedge clk) begin counter <= counter + 1; if (counter >= 10415) begin state <= nextstate; counter <=0; if (load) rightshiftreg <= {1'b1,data,1'b0}; if (clear) bitcounter <=0; if (shift) begin rightshiftreg <= rightshiftreg >> 1; bitcounter <= bitcounter + 1; end end end //state machine always @ (posedge clk) //always @ (state or bitcounter or transmit) begin load <=0; shift <=0; clear <=0; TxD <=1; case (state) 0: begin if (transmit) begin nextstate <= 1; load <=1; shift <=0; clear <=0; end else begin nextstate <= 0; TxD <= 1; end end 1: begin // transmit state if (bitcounter >=10) begin // check if transmission is complete or not. If complete nextstate <= 0; // set nextstate back to 0 to idle state clear <=1; // set clear to 1 to clear all counters end else begin nextstate <= 1; // set nextstate to 1 to stay in transmit state TxD <= rightshiftreg[0]; // shift the bit to output TxD shift <=1; // set shift to 1 to continue shifting the data end end default: nextstate <= 0; endcase end endmodule ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- The problem is that i have not been able to implement this without making use of button to initiate the data transfer. Without the use of button the communication between Nexys 4 Board and PC doesn't take place. I can only see the RX Led blinking on FPGA board but not the data on teraterm. Could you please help me to find the solution to this issue? Regards Manas
  18. Hi, I have read the possibilities of Xbee and used it using arduino Uno board. Now, I facing problem on how to interface this on Nexys 4 Artix 7 FPGA Board. Basically i'm confuse on how to proceed on FPGA board. I have already started looking on UART protocol and its implementation. Please help me out on how to proceed forward. With regards Manas
  19. Hi, I am using nexys 4 Artix 7 fpga. I want to access sensor data connected at JXADC Pmod port and the sensor output data I want to display on HTTP Server or in a web page.I already able to access GPIO pin through HTTPServer and turning on off fpga board leds.I added PmodACL2 code but it's showing error "invalid conversion from 'u32* {aka long unsigned int*}' to 'u32 {aka long unsigned int}' [-fpermissive] xspi_l.h /PmodWifiACL/src line 122 C/C++ Problem" I am facing problem in interfacing PmodACL2 with HTTPServer code for displaying sensor output at HTTPServer page or web page. Please help regarding that and if possible suggest needful resources because I have not prior experience with SDK and c++. Thanks, Dewang Shukla
  20. hello, I recently purchased the Nexys4 DDR and I am eager to get started, I noticed on the reference guide that it states: 17 Built-In Self-Test A demonstration configuration is loaded into the Quad-SPI flash device on the Nexys4 DDR board during manufacturing. The source code and prebuilt bitstream for this design are available for download from the Digilent website. I cannot seem to find this download page as it does not have a link (note: I underlined it to show its specified that it is available for download) can somebody please direct me to this file location please. Thank you so much in advance.
  21. hi guys ; please i want to use seven segment in nexys 4 board and i have a error i think from the constraints file i'm not understand how to use constraints file to define the seven segment this is the program and constraints file ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity sev_seg is Port ( CLKIN : in std_logic; an3 : inout std_logic; an2 : inout std_logic; an1 : inout std_logic; an0 : inout std_logic; seg : out std_logic_vector(6 downto 0)); end sev_seg; architecture Behavioral of sev_seg is signal CTR : STD_LOGIC_VECTOR(12 downto 0); begin Process (CLKIN) begin if CLKIN'event and CLKIN = '1' then if (CTR="0000000000000") then if (an0='0') then an0 <= '1'; seg <= "0101011"; -- the letter n an1 <= '0'; elsif (an1='0') then an1 <= '1'; seg <= "0101011"; -- the letter n an2 <= '0'; elsif (an2='0') then an2 <= '1'; seg <= "0001000"; -- the letter A an3 <= '0'; elsif (an3='0') then an3 <= '1'; seg <= "0000110"; -- the letter E an0 <= '0'; end if; end if; CTR<=CTR+"0000000000001"; if (CTR > "1000000000000") then CTR<="0000000000000"; end if; end if; -- CLK'event and CLK = '1' End Process; end Behavioral; ------------------------------------------------------------------------------------------------------ constraints file ##7 segment display ##Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA set_property PACKAGE_PIN L3 [get_ports {seg[0}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] ##Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name = CB set_property PACKAGE_PIN N1 [get_ports {seg[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] ##Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name = CC set_property PACKAGE_PIN L5 [get_ports {seg[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] ##Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD set_property PACKAGE_PIN L4 [get_ports {seg[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] ##Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE set_property PACKAGE_PIN K3 [get_ports {seg[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] ##Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF set_property PACKAGE_PIN M2 [get_ports {seg[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] ##Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG set_property PACKAGE_PIN L6 [get_ports {seg[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] ##Bank = 34, Pin name = IO_L16P_T2_34, Sch name = DP set_property PACKAGE_PIN M4 [get_ports dp] set_property IOSTANDARD LVCMOS33 [get_ports dp] ##Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0 set_property PACKAGE_PIN N6 [get_ports {an0}] set_property IOSTANDARD LVCMOS33 [get_ports {an0}] ##Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1 set_property PACKAGE_PIN M6 [get_ports {an1}] set_property IOSTANDARD LVCMOS33 [get_ports {an1}] ##Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2 set_property PACKAGE_PIN M3 [get_ports {an2}] set_property IOSTANDARD LVCMOS33 [get_ports {an2}] ##Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name = AN3 set_property PACKAGE_PIN N5 [get_ports {an3}] set_property IOSTANDARD LVCMOS ##7 segment display ##Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA set_property PACKAGE_PIN L3 [get_ports {seg[0}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] ##Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name = CB set_property PACKAGE_PIN N1 [get_ports {seg[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] ##Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name = CC set_property PACKAGE_PIN L5 [get_ports {seg[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] ##Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD set_property PACKAGE_PIN L4 [get_ports {seg[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] ##Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE set_property PACKAGE_PIN K3 [get_ports {seg[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] ##Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF set_property PACKAGE_PIN M2 [get_ports {seg[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] ##Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG set_property PACKAGE_PIN L6 [get_ports {seg[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] ##Bank = 34, Pin name = IO_L16P_T2_34, Sch name = DP set_property PACKAGE_PIN M4 [get_ports dp] set_property IOSTANDARD LVCMOS33 [get_ports dp] ##Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0 set_property PACKAGE_PIN N6 [get_ports {an0}] set_property IOSTANDARD LVCMOS33 [get_ports {an0}] ##Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1 set_property PACKAGE_PIN M6 [get_ports {an1}] set_property IOSTANDARD LVCMOS33 [get_ports {an1}] ##Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2 set_property PACKAGE_PIN M3 [get_ports {an2}] set_property IOSTANDARD LVCMOS33 [get_ports {an2}] ##Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name = AN3 set_property PACKAGE_PIN N5 [get_ports {an3}] set_property IOSTANDARD LVCMOS33 [get_ports {an3}] ______________________________________________________________________________________
  22. HI guys ; please i want a some help; i want to connect Nexys 4 board with RTLSDR receiver and get data from him and do processing in FPGA , some people tell me it is hard with VHDL and they propose to do this with microblaze , i need some help to do this , (advices , tutorial ....). thanks
  23. eli

    Nexys4 Ethernet Example

    hi, i tried working with this tutorial on vivado 2016.2 https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-getting-started-with-microblaze-servers/start?redirect=1 . but when i'm trying to "Generate Bitstream" , i get an error and many warnings. can't figure why, anyone can help??
  24. Juilan Daum

    Missing Oscillator

    Hi, I'm working with the Nexys 4 FPGA, trying to pass the 100 MHz clock from E3 to G1 (Pin JD3), and I'm seeing no output there. When I flip the board over, I noticed X2 is populated (looks like an 8 MHz oscillator), but X1 has no component, and it's the same size and form factor. Is X1 missing something? Thanks for any help!
  25. PALM

    PMOD AD1 on Nexys4

    Hi, I recently purchased a nexys 4 board and a Pmod AD1 to get short latency audio input to the fpga. Is there any vhdl example available to get audio samples from the AD1? the Digilent ressource center does not have any ... thanks, Pierre