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Found 19 results

  1. Hi, I really like the Nexys series boards, I've a Nexys2, a Nexys3 and a Nexys4 board. Artix-7 FPFAs a fine, but Kintex-7 are about a factor two faster. So I'd love to have an affordable Kintex-7 based board. There are now several Nexys variants. but why not a Nexys4 K7 with a XC7K70T or even XC7K160T. When I look at the FPGA cost a see XC7A100T-1CSG324C ~ $110 XC7K70T-1FBG484C ~ $120 XC7K160T-1FBG484C ~ $220 so a XC7K70T should be possible at a price tag still comparable to the current Nexys4 A7. Maybe somebody from Digilent can comment on this. Or users who'd like to buy such a board With best regards, Walter
  2. I tried the new Instant SoC from FPGA Cores on my Nexys 4 DDR (Nexys A7) board. Instant SoC is a C++ compiler that compiles C++ directly to a RISC-V processor and peripherals. The result is one vhdl file that I synthesized with Vivado. The only file I needed to add was the constraints file to map the signals to pins. The code implements a simple inclinometer. This is a description of what the code does: Sleeps 100 ms Read accelerations from the on board accelerometer using SPI Calculates angles using floating point math (atan, sqrt) Removes the zero offset that is reset using the center button. Print angles with one decimal point on UART Set the angles on 7 segment display Calculates an effect on the 16-leds. A led is “rolling” to the direction the board is leaning. Repeat A lot of the code was taken from Instant SoC class lib doc. The "hardware section", first in the main file defines the IO etc. In this case I created the following objects: ... int main(void) { //% hw_begin FC_IO_Clk Clk(100); FC_IO_Out LED(16); FC_IO_SPI accel(1000000,0,8); FC_IO_UART_TX uart_tx(115200,32); FC_IO_SegmentDisplay s7(8,8,0); FC_IO_In button_center; FC_System_Timer timer; //% hw_end uart_tx << "\r\nInclinometer demo using Nexys\r\n"; ... When compiling this it resulted in a VHDL file with the following port signals: ... entity nexys is port( Clk : in std_logic; LED : out std_logic_vector(15 downto 0); accel_SCLK : out std_logic; accel_MOSI : out std_logic; accel_MISO : in std_logic; accel_SSn : out std_logic; uart_tx : out std_logic; s7_seg : out std_logic_vector(7 downto 0); s7_sel : out std_logic_vector(7 downto 0); button_center : in std_logic ); end entity; architecture IMPL of nexys is ... And if you prefer Verilog there is also a Verilog header file generated: ... module nexys( input Clk, output [15:0] LED, output accel_SCLK, output accel_MOSI, input accel_MISO, output accel_SSn, output uart_tx, output [7:0] s7_seg, output [7:0] s7_sel, input button_center ); endmodule ... The system is free to download. I have attached the bit file (zipped) so it is possible to see what the C++ does. nexys.cpp nexys.xdc nexys_bit.zip
  3. Shahin

    Nexys 4 Ring Oscillator

    Hey guys, I want to implement a ring oscillator on my Nexys 4. Below is an image of the structure I want to implement and the code is also attached: Is it possible to just synthesize this and read the output of the counter or simply attach the output of the CUT to an oscilloscope and read the frequency? Thanks, Shahin source.zip
  4. Hello all, I bought the nexys 4 DDR, and since I am new I started with the basic tutorial blinky. Everything goes well until I get to step 8. "Synthesis, Implementation, and Bitstream Generation" The Synthesis ran successfully, and where it fails is at the bitstream generation. Since the Synthesis was completed I am assuming is not the verilog code, and is just some setting that I need to complete. The log gives the following error: ERROR: [DRC NSTD-1] Unspecified I/O Standard: 2 out of 2 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk, and led. ERROR: [DRC UCIO-1] Unconstrained Logical Port: 2 out of 2 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk, and led. WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: I googled the error and the query gave me 2 answers. The first one looks way way to complicated and to be honest I don't understand it. I got lost at the first step. The second answer is from digilent forums. In there the person asking said he fixed it, and he wrote this; "I solved this. I had input 'clk' in the source and 'CLK' in the constraints file". I am using the constrain file that I donwloaded digilent named "Nexys-4-DDR-Master.xdc" and in the clock I have CLK100MHZ and a commented out one called "clk100mhz". I tried changing in the verilog file to those names instead of clk, since the blinky tutorial said not to modify the constrain file and only uncomment. Please help this is like the most frustrating hello world I ever had to do. I attached my project files and constrain files in case anyone wants to look at it. blinky.zip Nexys-4-DDR-Master.xdc
  5. good day to all, my question is this: I am using the XADC of the Nexys 4 DDR, using the single channel mode, I want to sample at 1000 KSPS but using the IP CORE XADC Wizard it tells me that with these features the current conversion rate decreases to 961540 KSPS, I have searched the documentation of the XADC but I can not find a concrete answer to why this happens. If someone could help me, I would appreciate it.
  6. I am currently using nexys 4, I want to input console inputs to my VHDL design. I know that ISE uses a .ucf file where the inputs and outputs of the card are assigned, however my interest is not to use the inputs provided by the card and I do not know how to assign these inputs sent from an application, I would thank anyone who can help.
  7. Hi, I'm new to this. I want to know how to describe in VHDL the operation of the ADC of the Nexys 4 to view it in LEDs. Any suggestion?
  8. We use Nexys 4 DDR boards for testing our platform. While with most of the Windows host PCs there are no issues, with one of our clients' when the board is plugged in (using the supplied micro USB cable) it shows up as two COM ports under Windows's Device Manager. We suspect this is behind that we can't properly run Xilinx SDK programs on the board, the debugger looses the connection. Is it normal that the board shows up as two COM ports? (When the board is de-attached the ports disappear, so both are surely the single board.) If yes, can this cause issues? If now, how can we begin to troubleshoot the problem, what can possible be behind it? Thank you in advance!
  9. Dimitry

    Vivado filter project

    Hello, I'm new in FPGA and I'm trying to realize a filter using the FPGA Nexys 4 on Simulink. I have already done the Simulink circuit and export it to the Vivado Design sout as a project. Here I choose the right FPGA but i have problem with I/O Ports planning. My output of this project will be a filter which will realize the filtration of biological signal (ECG) which i will bring on JXAD input port on FPGA. Can somebody please help me with realization in Vivado and tell me, which output can be the best after the filtration? Your help means very much to me...
  10. I have a Digilent Nexys 4 board with me, and a medical device that provides streaming data via USB slave out, and I understand that my board has a USB HID, but it is connected to a PIC uC which converts it to PS/2 signal for me to use it. I was trying to implement a PS/2 controller to read this but then I came across this post on your forums where a Digilent technician said that video cameras are not supported, only mice and keyboards are. So I'd like to know how to connect a non mouse, non keyboard USB device to my board. This isn't an easy thing to Google so apologies if the answer was in the open. Regards
  11. Hi, I have developed a simple verilog program that reads a matrix from a text file, loads it into BRAM, performs some computation and then store the output back into BRAM. I have simulated the program and it works as expected. Now I want to test it on the FPGA, but I am not sure how to do that. 1- If I continue to use BRAM, how can I view the content of the BRAM after the execution is over to verify the output? 2- If I decided to use USB flash memory to read the matrix and write the result, how do I specify the names of the input/output files? There are a lot of resources that explain AXI USB and SPI using memory addresses, but how can I know the addresses of the input/output text files? Thanks! Wesson
  12. Just got a Nexys 4 DDR board for a class and the second I plugged it in, the busy light came on and it hasn't gone off yet and I get a message in Vivado when trying to connect it to the hw_server saying it may be locked by another hw_server?
  13. Hello!I am an electrical engineering student and I use a Digilent AC701 board, for my projects. I have similar problem as cclaunch had(topic:Fmc Carrier S6 Loading Config File To Flash ). I want to use a free and easy solution to burn my config program to the SPI Flash but I can't do it with the Adept. I want to do automatic boot from the flash anyhow. Is there any new solution for this problem(a don't want to use impact)? Is it possible that the Adept will support the SPI Flash programming?I thank you in advence for your reply.
  14. Hi I bought a Nexys 4 mainly due to the 8 digit and the amount of the resources the FPGA had in the Nexys 4 versus the Basys3. I did not read until later that a locked version of Vivado is with the Basys3. I am a novice at this technology. Does the locked version of Vivado that only works with Basys3 have the logic analyzer with it or the serial IO analyzer with it? What are the main differences between locked version and the downloaded webpack i have now? If it does have these tools in it, then these are tools that at least give me a better chance of success on a smaller version of my project, I need to reconsider my not purchasing the Basys in favor of purchasing the Nexys4. Thanks Rex
  15. Clint from WSU has posted some projects based on Vivado. User can use Basys 3 or Nexys 4 and develop the project in Vivado. http://www.eecs.wsu.edu/~ee214/projects.php
  16. Hi everyone, I have a Nexys4 board and I am trying to generate a simple program in VHDL using Vivado 2014.4 Webpack. When I get to the Generate Bitstream phase I get the following warning: ----------------------------- WARNING: [Drc 23-20] Rule violation (CFGBVS-1) Missing CFGBVS and CONFIG_VOLTAGE Design Properties - Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 ----------------------- The program apparently works OK even though there is this warning. I am using the constraints file provided by DIGILENT: http://digilentinc.com/Products/Detail.cfm?NavPath=2,400,1184&Prod=NEXYS4 where I have uncommented the clock signal, the 7 segment displays and the first switch. I have tried to solve this but I am new to FPGAs and there is an overwhelming amount of documentation. It would be great if someone could help me. I don't want to change anything and risk damage to the board. I see that the example project provided by Digilent also has the same warnings. Thanks in advance Andres
  17. Hi, I've been working for a while now to create a program which generates a specific signal. I think I may have succeeded but I don't know how to verify that. I was hoping that there would be a way to use the Diligent Adept software or Xilinx ISE to see what my board is outputting. Hardware/software; Im using A nexys 4 board, ISE 14.7, and adept 2. The code I have was generated by Matlab's hdl coder and the out puts are two 10-bit signals. Thanks.
  18. A customer asked if the Nexys 4 kit includes the micro USB cable to program the board. Here is my answer: The Nexys 4 includes the FPGA development board and the USB A to micro B cable in the DVD case. See the picture below.
  19. asmao

    PMOD as GPIO

    Hello, I'm currently using a Nexys 4 board and I would like to serially output and receive data. I was wondering if this could be done through a PMOD port? If so, how? Inside of my HDL design (I'm using Vivado 2014.2 and my HDL is in verilog) I'm asserting various PMOD ports yet whenever I try to measure the outputs I got nothing. My HDL looks something like this:assign JC1 = 1, JC2 = 0; Both JC1 and JC2 measure to 0. I've also tried the alternative names listed in the schematics (K2 and E7) as well as other PMOD interfaces. If I can't use the PMOD ports in this fashion, I was hoping to hear any suggestions? Thanks,Alvin