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  1. Hello, I receive my I2C Audio PMOD ( today and I want to use it with my ZYBO. My I2S transmitter look like this: library ieee; use ieee.std_logic_1164.all; entity I2S_Transmitter is generic ( DATA_WIDTH : integer := 32 ); port ( Clock : in STD_LOGIC; MCLK : out STD_LOGIC; Data_In : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); LRCLK : Out STD_LOGIC; DOUT : out STD_LOGIC; Reset : in STD_LOGIC; Empty : out STD_LOGIC
  2. I am trying to connect my PMOD MTDS to the Zybo Z7, without Arduino. I have integrated the IP files, connected it via block diagram, and set up a FAT32 microSD with the 2 files that are needed also. When trying to connect to Vivado I can seem to figure out how to get to the console for which I can do MTDS Firmware code so I can do a custom UI. Documentation does not help much with connecting this PMOD. Please advise if you're familiar thanks.
  3. I have successfully compiled, flashed, and ran the hdmi in example project in the digilent github repo. However, no matter the hdmi source I use, I cannot get the hdmi to connect to the Zybo dev board. The CRT monitor is displaying the VGA output, and I can change resolution and frame buffers. However, I always get an !HDMI unplugged! error on the uart output. My windows machine recognizes the "monitor" and I can change the resolutions on the windows side of things, but no matter the resolution I cannot get the connection to go through. See attached screenshot. This is very frustrating for me.
  4. Hello, When I following The Zynq Book Tutorials(exercises 5b) , I met a error unfortunately. It says that 'Timing constraints are not met.'. I have no idea how to solve it. Could anybody do me a favor. timing_1.rpx ------ More detail shows below:
  5. Hi, I am using windows OS and want to know the use of USB port on Zybo board. I have no idea how it works. Can I able to implement using verilog or I must need Zynq processor? I appreciate if anyone have sample project which will describe the use of USB port using zybo board on windows OS. BR ALI
  6. Hi, I have a recently buyed a Zybo board and wanted to use it with Vivado 15.1 on Windows 10 I installed the cable drivers but the USB cable did not appear in the Windows device manager. Only the Jungo Windriver is there. It seems as would the FTDI chip be invisible for Windows. So, I assumed it is either defect or misconfigured. Therefore I tried to use the FTDI tools like FT_Prog to check the FTDI chip on the USB port. But still no luck. This tool doesn't work. It complains that FTD2XX.dll is missing. This DLL will not be installed by the Xilinix cable driver fo
  7. Totally new to all this. 73 year old grandpa, retired engineer, returning to grad school, microelectronics concentration. Lots of technology catch-up to do. So, starting with VHDL. I must self-teach VHDL and need my first FPGA. Can someone help me understand these 3 possible choices for someone in my position: (1) Basys MX3 PIC32MX, (2) Nexys A7-100T, (3) Zybo Z7. Don't want to buy anything too complex, but I have to get the basics with ability to grow. Many questions about compatibility, accessories, programming... Can you help me get started?
  8. I am trying to make RAM work on my zybo; however, it keeps failing the memory test, I have tried additionally, I have tried setting up different "memory part" in the settings in vivado according to these reference manuals Do you know what I might be doing wrong?
  9. Hey, I have a very novice question and really just need a high level answer, but I'll get straight to the point! I'm using the Zybo z7-10 with Vivado and Vitis 2019.2. This is what I would like to do, and I'm trying to do it in VHDL: Write some data from software to control registers that I define Perform some processing on this data Use DMA to write some results to DDR I would like the firmware piece that does the processing to be a block in the BD. I've gone through many forums, and it seems at one time the preferred way was to package an IP. I found out about
  10. Hi all, You know how when you first power on the board, the LEDs cycle in a pattern and the HDMI TX displays a rainbow test pattern? I was wondering if the sources/a Vivado project for that behavior exists somewhere, it would be cool to see how all that is done. Thanks!
  11. Hello, I bought the Zybo-Z7-20 eval board. I downloaded the DMA project from repository and it ran fine in the EDK. So, far so good. However, when I started to re-run synthesis, there were error in the synthesis as to could not synthesize the Zynq part. Below is the error message from the synth log. I would appreciate anyone noticing this error showing how to get past it. Seems like I am missing some setup files or folder, not sure what .... ============================ Near the end of Error Log: ============================ couldn't open "i:/Rafi/Dropbox/Engr_con
  12. Hope you all are fine, I downloaded Digilent/Zybo-Z7-20-HDMI from I have upgraded the ip's, it was displaying output on monitor. Then I have created the ip of sobel edge detection and added the ip in block diagram. After solving some clocking issues, bitstream has been generated. After launching to sdk, when I Launch on Hardware (System Debugger), output doesn't display. Below is block diagram, please guide me
  13. I use a 10MHz clock and a 2-bit register to generate a 100 ns pulse at a frequency of 2.5 MHz(100 ns on, 300 ns off).The signal is output through an IOBFF into the pin JC1 (V15), which drives a 180 ohm resistor. According to the reference manual, JC is one of the 3 high speed PMODS, but despite this my rise and fall times are around 5-7 ns.The slew rate is set to "FAST" and the drive strength is set to "16".I want to decrease the rise and fall times to their absolute minimum value possible. The code for generating the pulse : reg [1 : 0] counter = 0; always @ (posedge clk) begi
  14. Is there any DSRC transceiver module (IEEE 802.11p), the wireless communication protocol for vehicles, that is compatible with FPGA board? I would like to interface it with Zybo board. Could someone provide input on this?
  15. Does the demo design ( support 1920x720 HDMI path-throught? The Product guide for dvi2rgb and rgb2dvi IP mentions that "Resolutions supported: 1920x1080/60Hz down to 800x600/60Hz (148.5 MHz – 40 MHz)" but I am not sure if the specific resolution 1920x720 is supported. Thank you
  16. Hi, apparently it is easy to damage something by playing around with the XADC-port (of a Zybo-Z7 in this case). I want to read the charging curve of a capacitor. How I thought this could be done I simulated in LTSpice: 300mv are much less than the maximum 1V and I added R5 and R3 because there are no preresisitors inside XADC-ports. I guess this way my hardware should survive the first time converting an analog voltage curve into digital value. But I'm, just guessing so the two questions I have about this are 1. Is this safe? 2. Is there a better way to do this? a
  17. hey there I am a beginner to zynq. I have bought a zybo board. I am using vivado version 2015.4. I followed the below link to add zybo board file to vivado: then I this tutorial: but it did not work. in this tutorial says: but when I select Hello world demo, I see the below attached image. it says that could you please tell me what I should do? thanks in a
  18. Hello All, I am having an issue with running the Master Polled example on I2C with the zynq. I have a base design that is set up and runs the self test and repeated start examples and completes them. My issue is that I hooked up an I2C sensor, added pullup resistors, and it is failing. The only thing I have changed in SDK is that I have found the address of my I2C sensor, 0x57, and put it in place of 0x55. I can place my block design and what not here for referencing. Update - I have assigned I2C pins to W19 and W20 to SCL and SDA respectively.
  19. Hi I want to utilize sdk to test echo server lwip,fpga program and run configration are done.However,in console,there are some lines make me confused. -----lwIP TCP echo server ------ TCP packets sent to port 6001 will be echoed back link speed: 1000 DHCP Timeout Configuring default IP of Board IP: Netmask : Gateway : TCP echo server started @ port 7 When I ping the board on PC,it displays "can't access the destination host" My board is Zybo.The hardware been built in vivado 2014.3.1 is a Zynq
  20. Hi all, New to the FPGA world as I was tasked a project to help familiarize myself with the programming and function of how FPGAs work. As you can all infer, I am in need of some help on a specific project that I am doing. I am using a ZYBO Zynq 7000 development board, and Vivado 2019.1. What I am trying to do is control an external sensor, or LED through some user interface. I have seen a lot of tutorials that use the on-board LEDs, and if you press a button, it displays that value in binary in a command terminal. My task that I was to do is be able to turn on and off an exter
  21. Hi everyone ! I'm working on the zybo board. There is a yocto linux on a SD card, and the system boot on the SD card. This works very well. Now I really enjoy if I could understand how to link vivado (to generate bitstream) and yocto ! I'm a little lost about this link. I read that some people say to use the layers meta-xilinx-tools ? Someone already use it ? I don't really understand how to use it, and how manage the boot.bin, u-boot, fsbl ... etc Could you help me please ? best regards, Yohan
  22. SDK fatal error:xgpio.h no such file or directory I am using: Vivado 2016.4 Design Tools Windows10 on a Lenovo Ideapad Zybo dev. board with the Zynq7020 While following the first exercise in The Zynq Book Tutorial. I encountered several errors but they seemed harmless enough since I was able to successfully create and export a bitstream. But now I am wondering if those warning and errors from the IP Integrator stage is causing my inability to build the project LED_test_tut_C.c code in the SDK, receiving fatal error:xgpio.h:No such file or directory. When lo
  23. Any & all help is appreciated with this thread. I am 100% new rookie to FPGA. I purchased the Digilent Zybo Z7: Zynq-7000 ARM/FPGA SoC Development Board (Zybo Z7-20 with SDSoC Voucher) My intentions are to crypto currency mine a new FPGA algo called Odocrypt created by the blockchain group Digibyte DGB. Here are a couple links to the info. DigiByteCoin Github Odocrypt Mining Software It will change every 10 days. Its supp
  24. Hello, I’m having problems with sending large amount of data from ZYBO to a computer. For example, when I tried to send image data (640x480) at the maximum baud rate, the computer didn’t receive all data. But when baud rate was set to 256000, all data were received. It seems like UART buffer is overflowing. How to solve this problem? Best regards, Toni
  25. Hello, I have a Zybo Board (Version 1 Rev. and I have a strange Issue with my XADC which samples the input for the channel AD7 on the channel AD14. Please take a look at my setup. I want to use the differential Channelpair 7 and 15 (like in the Photo - upper row VIn and lower row ground from my voltage source). My software gives me the results for channel 14 and 15 and the value for channel 7 stays constant even when I increase or decrease the input voltage. Only channel 14 and 15 change her values. I expect that channel 14 stays constant and channel 7 change his value. Temperature: