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Found 281 results

  1. I am following the steps outlined in https://reference.digilentinc.com/vivado/getting-started-with-ipi/start I am using a zybo-Z7-20 board and specifying VHDL. I have successfully completed the design and can modify the 'C' code in the xilinx SDK using the zynq processor. I am having trouble attempting to complete the same feat using a MicroBlaze processor. The fatal problem occurs in step 5.3 when generating the Bitstream. In various attempts the errors center around 2 unassigned ports. Here is the latest. [DRC NSTD-1] Unspecified I/O Standard: 2 out of 11 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. [DRC UCIO-1] Unconstrained Logical Port: 2 out of 11 logical ports have no user assigned specific location constraint (LOC). I have attached the full error and block design. ---- I wish to add a couple of comments regarding Vivado. In my installation on two different computers; in step 5.2 when defining the Top Module, the 5.2 recipe does not work for me on these two Windows installations. However, if one exits Vivado and restarts Vivado, the top module magically appears. However, if one starts Vivado from its desktop icon, Vivado get confused as to what is its project name. If one starts Vivado at this point from the file name in the project directory (ProjectName.xpr) the problem goes away. (See attachment VivadoProjName.JPG, project name is GettingStarted_3) GettingStarted_error.txt
  2. Currently we are using Nexys Video Development Board which is having many features and peripherals. Now we want to make our custom board with limited peripherals. We would like to use only 2 Configuration modes - JTAG Progamming and Quad-SPI Flash Memory Mode. We are not looking for SD Card and USB Programming mode. In Reference Manual Configuration Diagram, There is one PIC14 Controller available, We have confusion about is requirement? Is it necessary to have if we are not using SD Card and USB Progamming mode? It will be great help if you can direct us in this regard. We are not able to find technical support email address hence we are writing on this email address.
  3. Hello all. I'm a newbie to Vivado HLS (2018.3) and trying to add the Nexys 4 DDR board files in a new project, and it's not in the Device selection dialog list. I placed the board files in "Xilinx\Vivado\2018.3\data\boards\board_files" and it's there in Vivado, but not in Vivado HLS. How can I add the board files to Vivado HLS? Thank you!
  4. I plan on purchasing the Zybo z7-20 for prototyping a project I am working on. After looking at the documentation for the board it says that Vivado WebPack supports the Zybo z7 board and is fully compatible with Design Suite. I just want to make sure that Xilinx Vivado WebPack works with this board. Thanks
  5. Hi all, We are looking to use the Arty board for first tests on a machine vision system we are developing, which runs a 72 MHz parallel interface. For ease of testing I was planning to use the Arty board and its I/Os, but I see that it has 200 Ohm series resistors on each pin which will put a limit on the max allowed switching speed. Are there any specifications on the pins when it comes to speed? With 200 Ohms about 5-8 pF is maximum allowed after the resistor for a 72 MHz signal. Else, as I do not have the board yet, are the resistors easy to get to (silkscreen designators for correct identification) to replace the resistors manually with a lower value? Thank you for your time!
  6. Hello everyone, I am looking for an ADC and a DAC of at least 2 MSPs and a resolution greater than or equal to 12 bits. I do not want to use ADC or DAC with an FMC type interface (I do not have enough free pins on my FPGA card). A serial type interface (SPI) would be nice. Are there PMODs that have these characteristics? If not, can you recommend an ADC / DAC with these characteristics (> 2 MSPs and> 12 bit resolutions)? I have to process signals of frequency <= 10 kHz and send them to a DAC with a resolution of at least 12 bits and an acquisition speed of at least 2 MSPs. Thank you! Regards H
  7. So I have the BeagleWire FPGA cape for the BeagleBone Black and I want to send interrupts from the FPGA to the linux os on the BeagleBone every time a switch on the cape . The BeagleWire consists of the Lattice iCE40HX4K FPGA. I understand this is done through GPIO and that an interrupt request line has to be set up but I need specifics and a better explanation of how to actually code this is Verilog. I'm new to FPGAs, just starting out, so any help would be appreciated. Details regarding the BeagleWire including its open source software, can be found below: https://www.crowdsupply.com/qwerty-embedded-design/beaglewire https://github.com/pmezydlo/BeagleWire
  8. TireV

    Cmod S6 - Multilayer?

    Hello all together, I'm working on a CmodS6 board for my university course right now. It'd be helpful to now something about the layer design of the Board. I assume it's a multilayer PCB, so at least 1 layer between front and back side, but can anyone tell me something more about it? e.g. common ground plate yes/no? Hope these information are not somehow confidential or protected, then never mind my question :) Thanks for any input!
  9. Hi, I have designed an UART core without any flow control for use with FPGA devices when communicating with LabVIEW. I am looking for a way to receive (from FPGA to LabVIEW) data fast and correctly, hence I am investigating the following configurations for setting the VISA READ when to start or stop reading UART bytes: 1-with termination char: this is very tricky in the binary world as are the FPGAs, because it can trigger false stops sooner than expected. A solution will be to use a custom 3 termination chars like "/n/n/n" and LabVIEW will read till will receive this sequence. 2- by counting the received bytes and compare them with the expected number of bytes and the process the data. 3- using flow control. Which approach is better to be used? Or do you have another ideas? Thanks, V.M.
  10. Hi - I just tried to install the XUP USB-JTAG Programming Cable from diligent. I also have a Diligent Programming Cable. Centos can see both cables (see below) Vivado can see the Diligent programming cable but not the Xilinx one. Given the physical constraints of the installation only the Xilinx one will work. Are there any specific instructions to get the Xilinx cable going? $lsusb | grep "Xilinx/|Future" Bus 002 Device 003: ID 03fd:000d Xilinx, Inc. Bus 001 Device 006: ID 0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC
  11. Hello, I am new to ZYBO board. I am working on a project where I want to control a sensor from my ZYBO board using UART and receive the data from the sensor via SPI. I searched for the reference design, tutorials online to get started with, but I could not find any. Can anyone point me in the right direction where I can refer to and implement my work? THANK YOU. This is my aim as shown below. I want Zybo to be the main host, not my PC.
  12. YakirP

    Pmod wifi SDK problem

    Hi i'm using Vivado 2018.2 + Zedboard, my goal is to use the WiFiScan from the examples attached to Pmod WiFi folder. i have build the project in vivado section and exported it to SDK at that point i'm creating new application project, choose C++ project and select finish. i'm getting the following errors: flexible array member 'DHCPDG_T::options' not at end of 'struct DHCPMEM_T' DHCP.h ‪/proj_bsp/ps7_cortexa9_0/include/DEIPcK/utility‬ line 216 C/C++ Problem flexible array member 'DHCPDG_T::options' not at end of 'struct DHCPMEM_T' DHCP.h ‪/proj_bsp/ps7_cortexa9_0/libsrc/PmodWIFI_v1_0/src/DEIPcK/utility‬ line 216 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'class TCPSocket' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/include/DEIPcK/utility‬ line 145 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'class TCPSocket' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/libsrc/PmodWIFI_v1_0/src/DEIPcK/utility‬ line 145 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'class UDPSocket' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/include/DEIPcK/utility‬ line 145 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'class UDPSocket' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/libsrc/PmodWIFI_v1_0/src/DEIPcK/utility‬ line 145 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'struct DNSMEM_T' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/include/DEIPcK/utility‬ line 145 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'struct DNSMEM_T' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/libsrc/PmodWIFI_v1_0/src/DEIPcK/utility‬ line 145 C/C++ Problem thanks for the help
  13. I am using Atlys board (Spartan-6). It has Marvell Alaska Tri-mode PHY (the 88E1111). I want to establish Ethernet connection (GMII- 10/100/1000 Mbps) which can dynamically switch between these speeds depending upon the type of network switch (10/100/1000 Mbps). Currently I am trying Address swap example generated by the trimac 4.6 core and it works fine with 1000 Mbps switch. When I change the switch (100 Mbps this time), address swap example doesn't transmit back the packet. I am using Colasoft packet builder and Wireshark to send and check the packets. On observing further, I found that there is a Multiplexer which is deciding the clock for either 100 or 1000 Mbps mode. The select line of this MUX is 'speedis10100_int'. I tied this signal (speedis10100_int) to an LED and found that this select line is not changing on changing the Switch (1000 to 100 Mbps). I further tried driving this select line of MUX manually by a Slide switch. Then I can observe the clock (output of MUX) changing from 125 Mhz to 25 Mhz (when i slide the switch and change the network switch to 100mbps). But still the address swap example doesn't work at 100 Mbps. Inputs of the MUX are 1) 125 Mhz generated by clock generator and, 2) mii_tx_clk (25 Mhz coming from PHY) Thanks in advance. Deepak Verma
  14. I have connected an ov 7670 camera to my Basys 3 board and want to transmit the frame to a PC via the micro-usb port. I have tried UART serial communication, but the bit per second rate is simply not high enough to transmit a full 640 * 480 frame 15/30 times a second. I had the idea of implementing some sort of parallel communication, however I could not find any information or guides. I was wondering if anyone could help me out either with parallel communication, or suggesting a different method of transmitting frames to a PC. Thanks in advance.
  15. I believe the clock latency is the total time it takes from the clock source to an end point. PFA Whereas, the propagation delay would simply be the delay between the two edges, like an input output example below. PFA So in other words, does this mean propagation delay between clock signals is kind of a clock skew, which is measure of latency if one clock period capture? Thanks Tip
  16. Hello, I've been having a lot of fun with the VGA Pmod. I thought other forum members might appreciate a couple of tutorials I've produced with it. Part 1: Intro to VGA and basic animation: https://timetoexplore.net/blog/arty-fpga-vga-verilog-01 Part 2: Bitmap display using your own image: https://timetoexplore.net/blog/arty-fpga-vga-verilog-02 Both are written in pure Verilog, so it's (hopefully) easy to understand what's going on and adapt for your own projects. Feedback welcome, Will
  17. John1123

    ARTY FPGA

    Hi, I don't really know where to post this but I have a question. I am very new to FPGAs so this may seem as a very stupid question. i wanted to use my ARTY and read values from the analog IO and output the values through UART. I am familiar with setting up UART and microblaze but I have no idea how to use the analog IO. Any help will be kindly appreciated.
  18. I am trying to understand the waveform created by create_generated_clock with -edge option. Suppose I have master clock as create_clock 2 [get_ports DCLK] like PFA - master_clock.png I do create_generated_clock -name G3CLK -edges {5 7 10} -source DCLK [get_pins UAND0/Z] Assuming needed is first edge of generated clock is falling edge, it is inferred at 1ns (or 2) automatically and why not at 3? Why would that be? PFA generated_clock.png Thanks
  19. Which are the choices to learn about network message processing in FPGA? I would like to get a couple of FPGA cards, to allow students to learn about low latency network message processing. My assumption is that the Ethernet port must be connected directly to the FPGA. Is this correct? If that is correct, then it seems that low cost solutions like the Arm based Zinq are not appropriate, as the network port is connected to the ARM CPU, and not directly to the FPGA. So far, the only card I could find where this 'direct connect' is stated, is the NetFPGA 1G card, at around 1,500 usd, Are there any lower cost options?
  20. Hey Guys, Im trying to connect HC05 Bluetooth module to my arty board. For this reason, first I implemented a serial module to read data, then I connect an HC05 module to the Arty board via Pmode connectors (Pmod jb connectors): set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {UART_TX}]; set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {UART_RX}]; about serial port, I am 00% sure it works properly with baud rate 9600 because I checked it first with a USB port serial communication and it works perfectly. the program is as follow: I send 8-bit data and data value should be shown in bit format on the LED. As I said it works properly via normal USB serial port but it doesn't work with the HC05 module. Does anyone of you have an idea why? here is the VHDL code (as I stated serial interface module works properly with USB port): library ieee; use ieee.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity main is port( CLK : in std_logic; UART_TX : out std_logic; UART_RX : in std_logic; BLUE_LED : out std_logic_vector(3 downto 0); GREEN_LED : out std_logic_vector(3 downto 0); RED_LED : out std_logic_vector(3 downto 0); LED : out std_logic_vector(3 downto 0) ); end entity; architecture behaviour of main is component uart is port (CLK : in std_logic; UART_RXD : in std_logic; UART_DATA_READ : out std_LOGIC_VECTOR(7 downto 0); UART_READ_FLAG : out std_logic; UART_DATA_WRITE : IN STD_LOGIC_VECTOR(7 downto 0); response_is_ready : in std_logic; UART_TXD : out std_logic ); end component; signal clock : std_logic; signal data_send : std_logic_vector(7 downto 0); signal data_receive : std_logic_vector(7 downto 0); signal data_ready_to_send : std_logic; signal data_received : std_logic; signal LED_VALUE : std_logic_vector(3 downto 0); signal UART_RX_S : std_logic:='0'; signal UART_TX_S : std_logic:='0'; signal i_int : integer:=0; type LED_STATUS is (LED_ON,LED_OFF,CHANGE_COLOR,INIT); signal LED_STATE : LED_STATUS := INIT; begin inst_UART:uart port map( CLK => CLK, UART_RXD => UART_RX_S, UART_TXD => UART_TX_S, UART_DATA_READ => DATA_Receive, UART_DATA_WRITE => DATA_Send, response_is_ready => data_ready_to_send ); inst_proc:process(clk,DATA_Receive,LED_STATE) --variable i: integer:=0; begin if(rising_edge(clock)) then GREEN_LED<=DATA_Receive(3 downto 0); LED_VALUE<=DATA_Receive(7 downto 4); end if; end process; CLOCK<=CLK; LED<=LED_VALUE; UART_TX<=UART_TX_S; UART_RX_S<=UART_RX; end architecture; Thx
  21. Hello all, some months ago I had a Basys 2 Board that I perfectly could program via multisim, designing an schematic and then exporting the design. Now I have an Arty S7 on my hands and I would wish to do the same. I followed the tutorials: http://www.ni.com/tutorial/14871/en/ and https://reference.digilentinc.com/learn/programmable-logic/tutorials/program_fpgas_through_multisim/start An instance for the Arty S7 was created in multisim and it gave me the option to generate the VHDL file from the design (I haven't verified the file yet). Multisim won't give me the programming option. I checked the configuration files for others working boards and there is a missing line for programming, like Device ID etc. Mi question, does anybody has tested programming the arty s7 from multisim? if not is it possible? directions ? Best Regards, Edwin Marte
  22. tiago0297

    Axi DMA always busy

    Hi, I'm doing a project that uses AXI DMA. I already done my Ip Core, my Block Design e and my SDK code. The problem is that when my program reaches while(XAxiDma_Busy(&axiDma, XAXIDMA_DMA_TO_DEVICE)) it gets stuck. I'm using a Zedboard and Vivado 2017.4. I did a search, found out that it's a very popular problem, but I had no success solving it, so I'm posting here trying to get more help. I'm attaching my sources. Thank you srcs.zip
  23. Hi, I'm not able to fully understand the relation between the Board file and the Constraints file in Vivado. In my design I need to connect a custom IP block to a Pmod connector on a ZYBO board. I've loaded the XML board file provided by Digilent but now I'm not anymore able to customize the pins as i would do with a constraint file since it seem to me that the mapping it is now specified in the XML file. # Pmod connector JB set_property PACKAGE_PIN T20 [get_ports {d_out[0]}] set_property PACKAGE_PIN U20 [get_ports {d_out[1]}] set_property PACKAGE_PIN V20 [get_ports {d_out[2]}] set_property PACKAGE_PIN W20 [get_ports {d_out[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {d_out[*]}]Should I need to add a constraint file even if the Board port mapping is already specified by the board file? Is this a good practice? Thanks
  24. Hello, I am searching for new FPGA development board to replace old Virtex-5 OpenSPARC XUPV5 board (ML509) which retired. https://www.xilinx.com/support/university/boards-portfolio/xup-boards/DigilentXUPV5Board.html https://store.digilentinc.com/virtex-5-opensparc-fpga-development-board-ml509-retired/ What is the most similar board which is being sold now? Thank you.
  25. Hello, I am working on a dual core project with mailbox IP on a Arty Z7-10 board which has been acting inconsistently. In my project, 1st core is receiving data from FPGA and sending it through mailbox to the 2nd core; the 2nd core is supposed to receive and write them to the SD card. I need to write the data at 0.5 to 1 MB/s speed, so I can not read and write fast enough on one core. As an example to show the problem, I am writing a number to the card that is being incremented by one on a loop, and plot that versus the clock cycles. Supposedly, my output should look like a straight line which it does if I do all of this on one core. Now, If I use the mailbox to send the same value between two cores, and write it on the 2nd core, I am seeing gaps and overlaps in my data which I am pretty sure is because of Mailbox. Here are two examples of what is happening. If you zoom into the time = 1.0, you can see the following gaps, and overlaps. I have set the size of mailbox at 2048, and made sure that it never fills up by checking its status on every loop. So I wonder what could be the reason for these gaps and overlaps? Can't Mailbox IP transfer data consistently between two cores? Is there any other method for doing such jobs? Thanks, Mahdi