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Found 46 results

  1. Digilent The XUP Virtex 2 Pro Engineering Development Board, NOS On Ebay
  2. Digilent ZedBoard: Zynq-7000 ARM/FPGA SoC Development Board ENG On Ebay
  3. National Instruments Digilent NI myRIO 1900 Student Edition w/ box & accessories On Ebay
  4. Hello all, I am new in this forum. I am using a ZedBoard Zynq-7000 Development Board (part#: xc7z020clg484) and familiar with Verilog modules/test bench as beginner. I've created a top module with an output 8-bit bus (OUTPUT) and multiple inputs. My inputs are CLK (from main clock of the board), RESET (push button), ENA (ON/OFF switch), stpGo (stop and go push button). Inside my top module I've three sub-modules instantiated and connected to each other. I created a constraint file to connect all the ports to the necessary switches or buttons on my ZedBoard Zynq-7000. Here is my constraint file: # Clock Source - Bank 13 set_property PACKAGE_PIN Y9 [get_ports {CLK}]; # "GCLK" # ---------------------------------------------------------------------------- # User LEDs - Bank 33 set_property PACKAGE_PIN T22 [get_ports {OUTPUT[0]}]; # "LD0" set_property PACKAGE_PIN T21 [get_ports {OUTPUT[1]}]; # "LD1" set_property PACKAGE_PIN U22 [get_ports {OUTPUT[2]}]; # "LD2" set_property PACKAGE_PIN U21 [get_ports {OUTPUT[3]}]; # "LD3" set_property PACKAGE_PIN V22 [get_ports {OUTPUT[4]}]; # "LD4" set_property PACKAGE_PIN W22 [get_ports {OUTPUT[5]}]; # "LD5" set_property PACKAGE_PIN U19 [get_ports {OUTPUT[6]}]; # "LD6" set_property PACKAGE_PIN U14 [get_ports {OUTPUT[7]}]; # "LD7" # User Push Buttons - Bank 34 # ---------------------------------------------------------------------------- set_property PACKAGE_PIN P16 [get_ports {RESET}]; # "BTNC" set_property PACKAGE_PIN R16 [get_ports {stpGo}]; # "BTND" # ---------------------------------------------------------------------------- # User DIP Switches - Bank 35 # --------------------------------------------------------------------------- set_property PACKAGE_PIN F22 [get_ports {ENA}]; # "SW0" #set_property PACKAGE_PIN G22 [get_ports {SW1}]; # "SW1" # --------------------------------------------------------------------------- # IOSTANDARD Constraints # Note that the bank voltage for IO Bank 33 is fixed to 3.3V on ZedBoard. set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]]; # Set the bank voltage for IO Bank 34 to 1.8V by default. set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 34]]; # Set the bank voltage for IO Bank 35 to 1.8V by default. set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 35]]; # Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard. set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets stpGo_IBUF]; My constraint file is looking at my top-module ports only. I thought my other modules are internally connected and don't have to create constraint files for each of them separately. I am using Vivado 2018.2 software and I have attached the screenshots helping you to understand me better. Part#: xc7z020clg484-1 or ****-2 getting the same result. I restarted the Vivado and ran synthesize and implementation in order to generate Bitstream. Before all these steps I used this command to set Bitstream version check to "False" in my Tcl consul. After Bitstream generation was completed successfully (as system reported) I went to program my device but no Bitstream file was showing in dialog box to open. I browsed and selected a .bit file in my impl_1 folder called CountingLED.bit. I had the same error messages after I ran "Program". Please refer to images and let me know if I am not clear enough. Thank you for your helps in advance.
  5. If you hear of or author a textbook featuring a Digilent product, we want to know about it! So far, we have the following list compiled: Digital Design Using Digilent FPGA Boards Verilog/Active -HDL Edition by Haskell & Hanna Introduction to Digital Design Using Digilent FPGA Boards- VHDL Edition by Haskell & Hanna PIC32 Microcontrollers and the Digilent chipKIT: Introductory to Advanced Projects by Ibrahim Real Digital: A Hands-on Approach to Digital Design by Cole FPGA Prototyping by Verilog Examples: Xilinx Spartan-3 Version by Chu Getting Started with chipKIT: The Arduino Compatible PIC32 Based Module by Hellebuyck Synthesis and Optimization of FPGA-Based Systems by Sklyarov & Skliarova iLab Analog by Chen Yun Chao Digital Fundamentals by Floyd The Zynq Book by Crockett, Elliot, Enderwitz, Stewart Beginning C for Arduino by Purdum Electrical Engineering Practicum by Bowman FPGA Based System Design by Memon, Hassan & Memon Introduction to Electric Circuits 9th edition, by Jackson/Temple/Kelly
  6. National Instruments Digilent NI myRIO 1900 Student Edition w/ box & accessories On Ebay
  7. Xilinx Digilent Spartan-3 FPGA Device board On Ebay
  8. Digilent Spartan-3E Xilinx Starter Kit FPGA Development Board On Ebay
  9. Digilent Xilinx XUP Virtex-II Pro Development System On Ebay
  10. Hi everyone, I downloaded digilent.waveforms_3.2.6_armhf.deb and installed it on my system. The "dwfcmd" command is working fine and the python examples also work. Now I want to compile the C examples and I keep getting errors: analogin_trigger.c:(.text+0x74): undefined reference to `FDwfDeviceOpen' analogin_trigger.c:(.text+0x9c): undefined reference to `FDwfGetLastErrorMsg' analogin_trigger.c:(.text+0xd4): undefined reference to `FDwfAnalogInFrequencySet' analogin_trigger.c:(.text+0xec): undefined reference to `FDwfAnalogInBufferSizeSet' analogin_trigger.c:(.text+0x110): undefined reference to `FDwfAnalogInChannelEnableSet' analogin_trigger.c:(.text+0x128): undefined reference to `FDwfAnalogInChannelRangeSet' analogin_trigger.c:(.text+0x13c): undefined reference to `FDwfAnalogInTriggerAutoTimeoutSet' analogin_trigger.c:(.text+0x154): undefined reference to `FDwfAnalogInTriggerSourceSet' analogin_trigger.c:(.text+0x168): undefined reference to `FDwfAnalogInTriggerTypeSet' analogin_trigger.c:(.text+0x17c): undefined reference to `FDwfAnalogInTriggerChannelSet' analogin_trigger.c:(.text+0x190): undefined reference to `FDwfAnalogInTriggerLevelSet' analogin_trigger.c:(.text+0x1a4): undefined reference to `FDwfAnalogInTriggerConditionSet' analogin_trigger.c:(.text+0x1f4): undefined reference to `FDwfAnalogInConfigure' analogin_trigger.c:(.text+0x208): undefined reference to `FDwfAnalogInStatus' analogin_trigger.c:(.text+0x248): undefined reference to `FDwfAnalogInStatusData' analogin_trigger.c:(.text+0x2dc): undefined reference to `FDwfDeviceCloseAll' I used clang and gcc to build the analogin_trigger.c sample: clang analogin_trigger.c Where is my mistake?
  11. How to read a CSV file in script editor and plot in wavegenerator ?
  12. Is there a way to stop generating the temporary files in below directory while accessing hw_server using Digilent cable. We are using Vivado 2018.3 to access the HW. Ø /tmp/digilent-adept2- Ø /dev/shm/diligent-adept2-* For some reason, few of these files appear to become “stuck” in the locked position on occasion which is what causes the below error: TCF 14:00:21.002: jtagpoll: cannot get port description list: ftdidb_lock failed: FTDMGR wasn't properly initialized TCF 14:00:21.012: jtagpoll: cannot get port description list: JTAG device enumeration failed: Initialization of the DPCOMM library failed. …above Errors are generate when hw_server was ran before Quick Search suggested a driver issue but if I delete the tmp files then it works fine. Any suggestions would be appreciated! Thanks HJ
  13. Digilent Xilinx Spartan 3 Starter Board Includes JTAG3 w/SPI To Parallel Cable On Ebay
  14. XILINX Digilent Basys 2 Board - Spartan3E-250 FPGA Development Kit On Ebay
  15. Digilent Xilinx XUP Virtex-II Pro Development System On Ebay
  16. Dear Diligent AD2 team Please can you update your companies notes supporting Microsoft .net drivers which work with C# and and F# for the Analog Discovery 2 tool. It is a an excellent tool , but be even more excellent if could work and be used in the microsoft .net environment. This is a link to a previous forum post on the subject which used visual basic 6 from a while back. The original visual basic 6 example . From the time before .net happened >> I have taken this worked example and updated to get it to run with in visual studio 2017 .See enclosed attachment- It is failing to work properly due a. dll memory project fault in the .dll driver. The C++ source code for the .dll driver is also included in the attachment. My request is can Digilent fix the driver so that is usable in .net assemblies and is Memory safe . This is the reported run time fault when trying to access FDwfDeviceOpen in line of code : nRet = FDwfDeviceOpen(-1, hdwf) Fault report : System.AccessViolationException HResult=0x80004003 Message=Attempted to read or write protected memory. This is often an indication that other memory is corrupt. Source=<Cannot evaluate the exception source> StackTrace: <Cannot evaluate the exception stack trace> Thank you for considering this request
  17. I plan on purchasing the Zybo z7-20 for prototyping a project I am working on. After looking at the documentation for the board it says that Vivado WebPack supports the Zybo z7 board and is fully compatible with Design Suite. I just want to make sure that Xilinx Vivado WebPack works with this board. Thanks
  18. Digilent Electronics Explorer Board On Ebay
  19. Digilent chipKIT Network Shield - 2x CAN, Ethernet, 2x I2C, USB On Ebay
  20. Digilent Xilinx Research Labs XUP Virtex-II Pro Development System Board On Ebay
  21. Digilent Xilinx Research Labs XUP Virtex-II Pro Development System Board On Ebay
  22. Hello, I ordered a brand new Analog Discovery bundle directly from Digilent a few weeks ago for use in a college class, but every time I have attempted to build a simple circuit and connect the board to WaveForms, I consistently get one of the two attached errors. The components of the parts kit have been working fine but it seems like there is a problem with the amount of power being supplied to the Analog Discovery board itself. Any help would be greatly appreciated. Thanks, bucklc2
  23. Hello All of you I am trying to debug my code on picozed board . Board is successfully recognized in my college desktop PC but when i tried to connect it in my pc(vivado 2017.4 window 10) hardware manager . It give me error that no hardware is open . I use diligent JTAG-USB programming cable for debugging . I recheck drivers and found out that cable is also identified by PC. Please give me a suggestion what should i do. Below you can find the screenshots of device manager for driver installation and hardware manager status.
  24. Digilent Atlys Spartan 6 Xilinx FPGA Board 410-178 On Ebay
  25. Hello, Does PmodSD ( support SD mode of operation? Is it designed only to work with SPI mode as written in the reference manual? Please let me know Regards, Vinay Shenoy