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Found 126 results

  1. Hi! I've been playing with the low cost ESP8266 modules, that present a IP-over-WiFi as a serial device, and you use modem-like AT commands to control it. I've just put up a project that allows the FPGA to connect to my Wifi network, then send status message to a service that is listening on my Linux VM. It is all done using VHDL state machines (no software CPU), and could most probably be made a little more compact. Because the serial port is running at 9600 and the AT command based protocol overhead it is a pretty low bandwidth solution, but enough if you wanted to add some basic WiFi telemetry to a design. The ESP8266 module used was under $7 - http://www.seeedstudio.com/depot/WiFi-Serial-Transceiver-Module-w-ESP8266-p-1994.html You can find all the source on my Wiki at http://hamsterworks.co.nz/mediawiki/index.php/FPGA_ESP8266
  2. I tried to do this Pong game project https://github.com/CynicalApe/BASYS3-PONG and connect VGA to monitor. But monitor keeps flashing. Video im not sure if this problem appear because i have connected Basys3-> VGA adapter to hdmi -> wire hdmi to mini hdmi. Because my screen has only mini hdmi port.
  3. I am having layers of problems with the Pmod MicroSD. My ultimate goal is to get through the wifi example on youtube with a Basys 3. Today I am just trying to do the "hello world" demo for the micro SD Pmod. Issues: [Common 17-69] Command failed: BOARD_PART_PIN cannot be assigned to more than one port ["f:/microSD.srcs/sources_1/bd/microSD_bd/ip/microSD_bd_PmodSD_0_0/microSD_bd_PmodSD_0_0_board.xdc":7] I get this error for 4 pins set_property BOARD_PIN {JB7} [get_ports Pmod_out_pin7_t] set_property BOARD_PIN {JB8} [get_ports Pmod_out_pin8_t] set_property BOARD_PIN {JB9} [get_ports Pmod_out_pin9_t] set_property BOARD_PIN {JB10} [get_ports Pmod_out_pin10_t] Vivado does finish making the bitstream. I then push on incase it works anyway. In the SDK I get another error. 12:28:33 **** Incremental Build of configuration Debug for project uSD **** make all 'Building target: uSD.elf' 'Invoking: MicroBlaze g++ linker' mb-g++ -Wl,-T -Wl,../src/lscript.ld -L../../uSD_bsp/microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "uSD.elf" ./src/main.o -Wl,--start-group,-lxil,-lgcc,-lc,-lstdc++,--end-group c:/xilinx/sdk/2018.2/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld.exe: uSD.elf section `.text' will not fit in region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' c:/xilinx/sdk/2018.2/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld.exe: region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' overflowed by 159832 bytes collect2.exe: error: ld returned 1 exit status make: *** [uSD.elf] Error 1 12:28:35 Build Finished (took 1s.389ms) Without really knowing what I'm doing, I read the error and think I need to allocate more local memory to the microblaze. "overflowed by 159832 bytes" I then open up my block design and try to customize the microblaze but see no place in change the memory it is allocated. I used the address editor and increase the allocated memory for the dlmb to 128K and then the ilmb to 128K. If I try 256K for each the validation fails. Then after this I get a slightly better SDK error. 13:13:22 **** Auto Build of configuration Debug for project uSD **** make all 'Building file: ../src/main.cc' 'Invoking: MicroBlaze g++ compiler' mb-g++ -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/main.o" -I../../uSD_bsp/microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/main.d" -MT"src/main.o" -o "src/main.o" "../src/main.cc" 'Finished building: ../src/main.cc' ' ' 'Building target: uSD.elf' 'Invoking: MicroBlaze g++ linker' mb-g++ -Wl,-T -Wl,../src/lscript.ld -L../../uSD_bsp/microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "uSD.elf" ./src/main.o -Wl,--start-group,-lxil,-lgcc,-lc,-lstdc++,--end-group c:/xilinx/sdk/2018.2/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld.exe: uSD.elf section `.text' will not fit in region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' c:/xilinx/sdk/2018.2/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld.exe: region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' overflowed by 61528 bytes collect2.exe: error: ld returned 1 exit status make: *** [uSD.elf] Error 1 13:13:25 Build Finished (took 2s.724ms) My over flow is down to 61528 bytes. I am doing all this by following the IPI tutorial and just adding the PmodSD to it. here and here Thanks FBOARC PS I am using Vivado 2018.2 as that is the version in the tutorial.
  4. Hello I am attempting to follow this but I am confused about section 2.3. It says to place all the application code in DDR. The Basys3 has no external memory but for the SPI flash. From a SPI flash description from an Arty reference, it says but when I read the Xilinx answer record 63605, it says on step 5. Create helloworld application and link to DDR (in the linker script make sure that this application is executing from DDR) Can someone explain to me how to do this all in the SPI flash? Do I need to somehow set that up in my block design in? I do have the QSPI in my block design already but it is not available to me as an option in the linker script window.
  5. Tells me PmodWIFI is packaged with board value arty and to update my basys3 to the arty. I am confused. Well hang on a second. It finished generating a bitstream and I see no critical warnings in the project summary. In fact if I tell vivado to discard user generated messages in the messages window, the project has no indication of critical warnings at all. Still confused but closer to my goal.
  6. Hi there, I connected my Basys3 into my Ubuntu however no led turned on and my computer does not recognizes any device connected to it. Therefore, I'm afraid my FPGA has burned out or my USB-B connector is malfunctioning. Is it possible to change my USB-B part for a new one? Does Digilent provide any support for this kind of situation? Or will I have to buy another Basys 3? PS: I have already tried to connect it with a different cable, connect directly to a USB port in another computer as well, and none of these worked. Best regards, Igor Lima.
  7. I am completly new for the FPGA and basys3 development board. I have a project for Counter on the 7 segment displays on the board. We got 3 different layers as a design. cntr cntr_rtl cntr_top cntr_top_struc io_ctrl io_ctrl_rtl And in the project it has to diplay on the 7 segment controlled by the switches : count up / count down / hold / reset options: The priorities for these switches are: 1. reset 2. hold 3. count direction top level VHDL file cntr_top.vhd Port Name Direction Description clk_i In System clock (100 MHz) reset_i In Asynchronous high active reset sw_i(15:0) In 16 switches pb_i(3:0) In 4 buttons ss_o(7:0) Out Contain the value for all 7-segment digits ss_sel_o(3:0) Out Select a 7-segment digit io_ctrl clk_i In System clock (100 MHz) reset_i In Asynchronous high active reset cntr0_i(n:0) In Digit 0 (from internal logic) cntr1_i(n:0) In Digit 1 (from internal logic) cntr2_i(n:0) In Digit 2 (from internal logic) cntr3_i(n:0) In Digit 3 (from internal logic) sw_i(15:0) In 16 switches (from FPGA board) pb_i(3:0) In 4 buttons (from FPGA board) ss_o(7:0) Out to 7-segment displays of the FPGA board ss_sel_o(3:0) Out Selection of a 7-segment digit swclean_o(15:0) Out 16 switches (to internal logic) pbclean_o(3:0) Out 4 buttons (to internal logic) cntr.vhd clk_i In System clock (100 MHz) reset_i In Asynchronous high active reset cntrup_i In Counts up if signal is ‘1’ cntrdown_i In Counts down if signal is ‘1’ cntrreset_i In Sets counter to 0x0 if signal is ‘1’ cntrhold_i In Holds count value if signal is ‘1’ cntr0_o(n:0) Out Digit 0 (from internal logic) cntr1_o(n:0) Out Digit 1 (from internal logic) cntr2_o(n:0) Out Digit 2 (from internal logic) cntr3_o(n:0) Out Digit 3 (from internal logic) I will attach also the file to the attachment. Now my code is working and do all the funcitionality correct but there is only one issue which is the DEBOUNCE code part. I didnt use the clk signal for the code and i have to change it. The certain given clock signal has to be used. So can any be give me suggestions how i can correct the debounce concept in the code. io_ctrl_rtl.vhd -code down below: library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; architecture rtl of io_ctrl is constant COUNTVALUE : std_logic_vector(16 downto 0):= "01100001101010000"; signal s_enctr : std_logic_vector(16 downto 0):="00000000000000000"; signal s_2khzen : std_logic :='0'; signal s_1hzen : std_logic :='0'; signal s_2khzcount : std_logic_vector(3 downto 0) := "0000"; signal swsync0 : std_logic_vector(15 downto 0):="0000000000000000"; signal pbsync0 : std_logic_vector(3 downto 0):="0000"; signal swsync1 : std_logic_vector(15 downto 0):="0000000000000000"; signal pbsync1 : std_logic_vector(3 downto 0):="0000"; signal swtmp : std_logic_vector(15 downto 0):="0000000000000000"; signal pbtmp : std_logic_vector(3 downto 0):="0000"; signal swdebounced : std_logic_vector(15 downto 0):="0000000000000000"; signal pbdebounced : std_logic_vector(3 downto 0):="0000"; signal s_ss_sel : std_logic_vector(3 downto 0) := "0000"; signal s_ss : std_logic_vector(7 downto 0) := "00000000"; begin -- rtl ----------------------------------------------------------------------------- -- -- Synchronize the inputs -- ----------------------------------------------------------------------------- p_sync: process (clk_i, reset_i) begin if reset_i = '1' then swsync0 <= (others => '0'); pbsync0 <= (others => '0'); swsync1 <= (others => '0'); pbsync1 <= (others => '0'); elsif clk_i'event and clk_i = '1' then swsync0 <= sw_i; pbsync0 <= pb_i; swsync1 <= swsync0; pbsync1 <= pbsync0; else null; end if; end process; ----------------------------------------------------------------------------- -- -- Generate 1 KHz enable signal. -- ----------------------------------------------------------------------------- p_slowen: process (clk_i, reset_i) begin if reset_i = '1' then s_enctr <= (others => '0'); s_2khzen <= '0'; elsif clk_i'event and clk_i = '1' then if s_enctr = COUNTVALUE then -- When the terminal counter is reached, set the release flag and reset the counter s_enctr <= (others => '0'); s_2khzen <= '1'; s_2khzcount <= std_logic_vector(to_unsigned(to_integer(unsigned( s_2khzcount )) + 1, 4)); else s_enctr <= std_logic_vector(to_unsigned(to_integer(unsigned( s_enctr )) + 1, 17)); -- As long as the terminal count is not reached: increment the counter. if s_2khzen = '1' then s_2khzen <= '0'; end if; end if; if s_2khzcount = "1010" then s_1hzen <= not s_1hzen; s_2khzcount <= "0000"; end if; end if; end process p_slowen; ----------------------------------------------------------------------------- -- -- Debounce buttons and switches -- ----------------------------------------------------------------------------- p_debounce: process (s_1hzen, reset_i) variable dbouncecntr : integer:=0; begin if reset_i = '1' then swdebounced <= "0000000000000000"; pbdebounced <= "0000"; dbouncecntr :=0; -- Change clocking the process with signal from sens list. else if (dbouncecntr = 0) then swtmp <= swsync1; pbtmp <= pbsync1; dbouncecntr := dbouncecntr + 1; elsif (dbouncecntr = 1) then if (swtmp = swsync1) then swdebounced <= swsync1; end if; if (pbtmp = pbsync1) then pbdebounced <= pbsync1; end if; dbouncecntr := 0; end if; end if; end process p_debounce; swclean_o <= swdebounced; pbclean_o <= pbdebounced; ----------------------------------------------------------------------------- -- -- Display controller for the 7-segment display -- ----------------------------------------------------------------------------- p_displaycontrol: process (clk_i, reset_i) variable v_scancnt : std_logic_vector(1 downto 0):= "00"; variable v_output : std_logic_vector(3 downto 0):="0000"; begin if reset_i = '1' then v_scancnt := "00"; s_ss <= "00000000"; elsif clk_i'event and clk_i = '1' then if s_2khzen = '1' then case v_scancnt is when "00" => v_output := cntr0_i; s_ss_sel <= "0001"; when "01" => v_output := cntr1_i; s_ss_sel <= "0010"; when "10" => v_output := cntr2_i; s_ss_sel <= "0100"; when "11" => v_output := cntr3_i; s_ss_sel <= "1000"; when others => v_output := "1111"; s_ss_sel <= "0001"; end case; case v_output is --ABCDEFG, when "0000" => s_ss <= "11111100"; --0 when "0001" => s_ss <= "01100000"; --1 when "0010" => s_ss <= "11011010"; --2 when "0011" => s_ss <= "11110010"; --3 when "0100" => s_ss <= "01100110"; --4 when "0101" => s_ss <= "10110110"; --5 when "0110" => s_ss <= "10111110"; --6 when "0111" => s_ss <= "11100000"; --7 when "1000" => s_ss <= "11111110"; --8 when "1001" => s_ss <= "11110110"; --9 when others => s_ss <= v_scancnt & "000000"; end case; if v_scancnt = "11" then v_scancnt := "00"; else v_scancnt := std_logic_vector(to_unsigned(to_integer(unsigned( v_scancnt )) + 1, 2)); end if; else null; end if; else null; end if; end process p_displaycontrol; ss_o <= not s_ss; ss_sel_o <= not s_ss_sel; end rtl; The code for : cntr_top_struc.vhd library IEEE; use IEEE.std_logic_1164.all; architecture rtl of cntr_top is component cntr -- component of cntr port (clk_i: in std_logic; -- 100 MHz system clock reset_i: in std_logic; -- async high active reset cntrup_i : in std_logic; --counts up if signal is '1' cntrdown_i : in std_logic; --counts down if signal is '1' cntrreset_i : in std_logic; --sets counter to 0x0 if signal is '1' cntrhold_i : in std_logic; --holds count value if signal is '1' cntr0_o: out std_logic_vector(3 downto 0); -- Digit 0 (from internal logic) cntr1_o: out std_logic_vector(3 downto 0); -- Digit 1 (from internal logic) cntr2_o: out std_logic_vector(3 downto 0); -- Digit 2 (from internal logic) cntr3_o: out std_logic_vector(3 downto 0)); -- Digit 3 (from internal logic) end component; component io_ctrl ---- component io_crtl port (clk_i: in std_logic; -- 100 MHz system clock reset_i: in std_logic; -- async high active reset cntr0_i: in std_logic_vector(3 downto 0); -- Digit 0 (from internal logic) cntr1_i: in std_logic_vector(3 downto 0); -- Digit 1 (from internal logic) cntr2_i: in std_logic_vector(3 downto 0); -- Digit 2 (from internal logic) cntr3_i: in std_logic_vector(3 downto 0); -- Digit 3 (from internal logic) swclean_o: out std_logic_vector(15 downto 0); pbclean_o: out std_logic_vector(3 downto 0); ss_o: out std_logic_vector(7 downto 0); -- Contain the Value for All 7-Segment Digits ss_sel_o: out std_logic_vector(3 downto 0); -- Select a 7-segment digits pb_i: in std_logic_vector(3 downto 0); --4 Buttons sw_i: in std_logic_vector(15 downto 0) ); --16 Switches end component; -- Declare the signals that are used to connect the submodules. signal s_cntr0 : std_logic_vector(3 downto 0); signal s_cntr1 : std_logic_vector(3 downto 0); signal s_cntr2 : std_logic_vector(3 downto 0); signal s_cntr3 : std_logic_vector(3 downto 0); signal s_cntrup : std_logic; signal s_cntrdown : std_logic; signal s_cntrreset : std_logic; signal s_cntrhold : std_logic; signal s_overflow : std_logic_vector(11 downto 0); begin --Instantiate the counter that is connected to the IO-Control i_cntr_top1 : cntr port map (clk_i => clk_i, reset_i => reset_i, -- cntrdir_i => s_cntrdir, --swsync_o(13); cntrup_i => s_cntrup, --swsync_o(13); cntrdown_i => s_cntrdown, --swsync_o(12); cntrreset_i => s_cntrreset, --swsync_o(15), cntrhold_i => s_cntrhold, --swsync_o(14), cntr0_o => s_cntr0, cntr1_o => s_cntr1, cntr2_o => s_cntr2, cntr3_o => s_cntr3); --Instantiate the IO control to which it is connected i_io_ctrl : io_ctrl port map (clk_i => clk_i, reset_i => reset_i, swclean_o(12) => s_cntrdown, swclean_o(13) => s_cntrup, swclean_o(15) => s_cntrreset, swclean_o(14) => s_cntrhold, swclean_o(11 downto 0) => s_overflow(11 downto 0), cntr0_i => s_cntr0, cntr1_i => s_cntr1, cntr2_i => s_cntr2, cntr3_i => s_cntr3, ss_o => ss_o, ss_sel_o => ss_sel_o, sw_i => sw_i, pb_i => pb_i); end rtl; Please waiting for your suggestions. Any help would be great appricated thanks for all. here down below example for debounce but couldnt find to way to implement. ----------------------------------------------------------------------------- -- -- Debounce buttons and switches -- ----------------------------------------------------------------------------- p_debounce: process (clk_i, reset_i) begin -- process debounce if reset_i = '1' then -- asynchronous reset (active high) elsif clk_i'event and clk_i = '1' then -- rising clock edge end if; end process p_debounce; swsync_o <= swsync; pbsync_o <= pbsync; ------------------------------------------------------------ Final Project-Decimal Count -1Hz.rar
  8. Hello, I just bought 35 BASY3 FPGA boards for our Digital Systems class and need to install Vivado Design Suite in 30 computers. However I noticed during the installation process a window prompts on the "Select Installation Type" I have to enter USER ID and PASSWORD. I would like to know if there is a way around to having to create 30 accounts in order to install on 30 computers. I suppose I can try to install using 1 account on all 30 computers. Please help me with the best way to install Vivado Design Suite for my class. Thank you, Marco
  9. It is possible to program the Basys3 to be used as a motherboard diagnostics card ?
  10. Hello, Merry Christmas hope you guys are doing great. I am a beginner in digital design course and i want to implement this xadc demo project from digilentinc reference on my Basys3 FPGA. I'm having problems on the step 4 which is running the project as i can't figure the physical connections to connect to the JAXDC port on FPGA. Can someone confirm if the connections i have done in this picture are right? One last question. When you open the XADC Basys3 Demo project and see its constraints, only package pins i don't understand are these A12,B13 ones. Where are they located on FPGA? I'm assuming there are some internal connections like seven segment decoder have. Any help appreciated. Thank You. Regards, Zain
  11. I'm still relatively new to Verilog and FPGA programming, so I've been struggling quite a bit with this one. The goal of the project here is to play a super basic game of 'blackjack' and I can't quite seem to get the system to work. As a note: The game goal is to get to 21, but a number reasonably high and close to 21 could still win the game based on what the Dealer has. The first few if - else if statements are there to interpret the card input from switches on the basys3, and then decide how much to add to the count based on the 'card' input. The latter if - else statement is there to output either an 'H' or an 'S' to the 7-segment display in order to output whether the player should 'hit' and recieve another card, or if that person should 'stay' and just hold onto the cards they have. For some reason, the board only displays the 'H' value on the 7 segment display, and I have no way to find out if the count is actually incrementing in the program since I can't figure out how to test this outside of the board. Any assistance would be greatly appreciated. As a note: I have checked the constraints file, and everything looks correct. blackjack.v verilog file: module BlackJack(input clk, ace, four, five, six, eight, jack, reset, output clk_slow, reg A, B, C, D, E, F, G, H, wire segEn, segEnd); //slow clock code parameter clkbit = 27; reg [clkbit:0] clk2 = 0; [email protected](posedge clk) begin clk2 <= clk2+1; end assign clk_slow = clk2[clkbit]; reg count = 0; assign segEn = 0; // enable for the 7-segment display assign segEnd = 1; always @(posedge clk_slow) begin if (count <= 10) //states from start to 10 - card decisions made here begin if (ace) count <= count + 11; //adds 11 else if (four) count <= count + 4; else if (five) count <= count + 5; else if (six) count <= count + 6; else if (eight) count <= count + 8; else if (jack) count <= count + 10; else count <= count; end else if (count <= 11) // states from 11 to 17 begin if (ace) count <= count + 1; //adds 1 else if (four) count <= count + 4; else if (five) count <= count + 5; else if (six) count <= count + 6; else if (eight) count <= count + 8; else if (jack) count <= count + 10; else count <= count; end else if (reset) begin count <= 0; end else begin count <= count; end if (count < 17) begin F <= 1'b0; B <= 1'b0; G <= 1'b0; E <= 1'b0; C <= 1'b0; A <= 1'b1; D <= 1'b1; end else begin A <= 1'b0; F <= 1'b0; G <= 1'b0; C <= 1'b0; D <= 1'b0; B <= 1'b1; E <= 1'b1; end end
  12. Hello, I'm a student and currently working on my final project including Basys 3 board and wifi pmod. I'm trying to get started working with the module to understand how it works. This is my first project working with Pmods. I've been using the Getting Started with Digilent Pmod IPs tutorials. I added the newest Vivado library including the PmodWifi IP and I bulit a block design with the MicroBlaze and other GPIO IPs. I followed the instructions of the tutorials and got to the part of validating the design, there I got a warning saying few of the wifi pmod pin are not connected. I've got a few other warnings and errors so I really don't understand what went wrong. If anyone know what the issue is and can help me, that would be awesome! Also I'm looking for an example project for wifi pmod using Microblaze to learn from. I'm attaching some screenshots of my project. thanks, Netanel.
  13. Hello, I new on Basys 3, and I need some examples for programming FPGA. In the resource center there are a lot of them, but the examples are written in verilog. I am using VHDL, so the questión is: Is there the same examples like the resource center written in VHDL?
  14. I am learning how to operate an FPGA, and I have to input a signal (which in itself is the output of a discriminator), and analyze it through a Basys3 FPGA. Looking at the available ports on the board, I'm guessing that it could be done using the Pmod ports, but even after hours of googling and going through the manuals, I failed to know which data ports to use, and how to read the signal after I've input it through the board. I've got references to some boards, in which GPIO ports are explicitly labelled, but I don't see any such labeling on the Basys3. So, it'd be really helpful if someone can provide me with any insight regarding this. Any other references or links would also be greatly appreciated. I've already gone through the basic tutorials (like lighting the led using the switch. I just want to know how to use the input ports, and analyze my signal. Thank You
  15. I am working in an DSP algorithm, I have generated the bitstream for that algorithm and dumped into FPGA basys 3 board (the output of the algorithm is of 16-bit wide and consists of 100 samples). Now, I need to view the waveform with the help of Waveforms software and analog discovery kit. So, how it can be done? Can anybody provide me some video or anyother material that can solve the problem. #So far information obtained# In the material "Basys 3™ FPGA Board Reference Manual Overview" page no. 18, since, my data is of 16-bit wide I have connected pmod pins JB1 to JB4 to analog discovery pins 0 to 3 and JB7 to JB10 to analog discovery pins 4 to 7 to transfer first 8-bit. Similarly, JC1 to JC4 and JC7 to JC10 are connected to the 8 to 11 and 12 to 15 no pins of analog discovery. Is the connection is ok? What will be other connections needed?
  16. I want to send 8 bit data from FPGA to PC, 9600 baudrate, 8 bit data, 1 start&stop bit, no parity. I did coded my Basys3 Fpga and connected to PC. By using Tera Term, wanted to see how it works out. But probably something big I'm missing out. I just wrote a transmitter code and somewhere I saw that some people used button&top modules too. Do I need them to see a 8-bit data's ASCII equivalent on my PC? How can I handle? library ieee; use ieee.std_logic_1164.all; entity rs232_omo is generic(clk_max:integer:=10400); --for baudrate port( clk : in std_logic; rst : in std_logic; start : in std_logic; input : in std_logic_vector(7 downto 0); done : out std_logic; output : out std_logic; showstates: out std_logic_vector(3 downto 0) ); end entity; architecture dataflow of rs232_omo is type states is (idle_state,start_state,send_state,stop_state); signal present_state,next_state : states; signal data,data_next : std_logic; begin process(clk,rst) variable count : integer range 0 to clk_max; variable index : integer range 0 to 10; begin if rst='1' then present_state<=idle_state; count:=0; data<='1'; elsif rising_edge(clk) then present_state<=next_state; count:=count+1; index:=index+1; data<=data_next; end if; end process; process(present_state,data,clk,rst,start) variable count : integer range 0 to clk_max; variable index : integer range 0 to 10; begin done<='0'; data_next<='1'; case present_state is when idle_state => showstates<="1000"; data_next<='1'; if start='1' and rst='0' then count:=count+1; if count=clk_max then next_state<=start_state; count:=0; end if; end if; when start_state => showstates<="0100"; data_next<='0'; count:=count+1; if count=clk_max then next_state<=send_state; count:=0; end if; when send_state => showstates<="0010"; count:=count+1; data_next<=input(index); if count=clk_max then if index=7 then index:=0; next_state<=stop_state; else index:=index+1; end if; count:=0; end if; when stop_state => showstates<="0001"; count:=count+1; if count=clk_max then next_state<=idle_state; done<='1'; count:=0; end if; end case; end process; output<=data; end architecture; Constraints: set_property PACKAGE_PIN V17 [get_ports {input[0]}] set_property PACKAGE_PIN V16 [get_ports {input[1]}] set_property PACKAGE_PIN W16 [get_ports {input[2]}] set_property PACKAGE_PIN W17 [get_ports {input[3]}] set_property PACKAGE_PIN W15 [get_ports {input[4]}] set_property PACKAGE_PIN V15 [get_ports {input[5]}] set_property PACKAGE_PIN V14 [get_ports {input[6]}] set_property PACKAGE_PIN W13 [get_ports {input[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[0]}] set_property PACKAGE_PIN L1 [get_ports {showstates[3]}] set_property PACKAGE_PIN P1 [get_ports {showstates[2]}] set_property PACKAGE_PIN N3 [get_ports {showstates[1]}] set_property PACKAGE_PIN P3 [get_ports {showstates[0]}] set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] set_property PACKAGE_PIN R2 [get_ports rst] set_property PACKAGE_PIN T1 [get_ports start] set_property IOSTANDARD LVCMOS33 [get_ports start] set_property IOSTANDARD LVCMOS33 [get_ports rst] set_property IOSTANDARD LVCMOS33 [get_ports done] set_property IOSTANDARD LVCMOS33 [get_ports output] set_property PACKAGE_PIN V3 [get_ports done] set_property PACKAGE_PIN V13 [get_ports output] My testbench simulation got attached. And on-board, apparently I stuck with 'idle_state'. For any kind of help, I thank y'all in advance.
  17. Hi, I have been familiarizing myself with VHDL and FPGAs in general with the Digilent Basys3 board. Recently I have tried incorporating the Microblaze in to my design just to familiarize myself with it. I have created a simple block diagram where I connect a custom AXI-stream counter to an AXI-DMA block. The counter just streams incrementing numbers and adds the tlast signal to generate frames. My purpose is to develop a minimum working example on AXI-DMA transfer. I plan to transfer x-number of samples generated by the AXI-stream counter with the AXI-DMA to a BRAM memory. On programming the AXI-DMA core I have followed the Xilinx manual PG021 https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf section Direct Register Mode (Simple DMA) on page 71. Initializing the DMA works. However, after sending the transfer command to the DMA no transaction happens. I wonder whether the problem is in my C-code or the block diagram. I have verified with the vivado ILA that the counter is working and produces a stream of data. In addition I have tied tkeep port to logical high on the s2mm port on the DMA. Is it possible I have forgotten something else? Any suggestions will be warmly welcomed. top_module.pdfAXI_DMA_minimum_example.c
  18. fpga_babe

    HID protocol on Basys3

    Hi, I am using Basys3 board and I want to write a RTL module in FPGA to get the character from USB Keyboard. From the Digilent reference of basys3, if the FPGA side only receive the data from Keyboard, then the PS_CLK and PS_DAT ports can be as input direction. My question is that, to receive the keycode from a keyboard, do we need to send configuration to Keyboard before hand ?
  19. Hello everybody, I am having a problem with the binary counter v12.0 reset SCLR signal, when implementing the Xilinx University Programme, Lab9 Project 3.1, 2015x (1). Environment: OS: Linux (Arch Linux) Xilinx Vivado 2018.3 Digilent Basys3 develoment board Verilog HDL Problem description: The project works as expected (counts up to 5 minutes, 0,1 second resolution), the exception is the counter reset button (BTNC, U18) is pressed it only stops the counting, when released, the counter is not reset, instead it keeps counting where it stopped. I am using the Vivado IP Catalog for generating the clock signal and the 4 binary counters(2) used on each 7-Segiment display digit. The Verilog code and constraint file are attached. The binary counter configuration: Implementing using: Fabric Output width: 4 [3:0] Increment Value (Hex): 1 Restrict Count (Hex): 4, 5, 9, 9 (7seg from left ro right) Count Mode: UP Clock Enable (CE): Checked Synchronous Clear(SCLR): Checked Init Value:(Hex): 0 Synchronous Controls and Clock Enable(CE) Priority: Sync Overrides CE Latency Configuration: Manual, 1 Feedback Latency Configuration: Manual, 0 I suspect I am overseeing/forgetting somewhere a simple detail. Any help/clarification is appreciated. Cheers, Rafael. (1) https://www.xilinx.com/support/documentation/university/Vivado-Teaching/HDL-Design/2015x/Verilog/docs-pdf/lab9.pdf (2) https://www.xilinx.com/support/documentation/ip_documentation/counter_binary/v12_0/pg121-c-counter-binary.pdf lab9_3_1.v Basys-3-Master.xdc
  20. Hi all: I'm new to both Vivado and the Basys3 board. I've been working thru the initial tutorials to get myself familiar with the software and the board. The very 1st tutorial, Getting Started with Vivado, went fine. Everything worked as advertised. The problem I've run into is with the 2nd tutorial, Basys 3 Programming Guide Tutorial (https://reference.digilentinc.com/learn/programmable-logic/tutorials/basys-3-programming-guide/start). I have the latest version of Vivado (2018.3) and the tutorial was built with 2015.1. The tutorial even has a zip file to download both the sw_led.v file and a Basys3_sw_Demo.xdc constraint file. After downloading the files, building the project, then running the synthesis I get 26 critical warnings that cause the Implementation and Generate BitStream to fail. 22 of the critical warnings are "V17 is not a valid site or package pin name" (and each of the following 21 warnings change the "V17" to the next pin name in the constraint file. (I've checked the schematic and the Pin Names ARE VALID) The next critical warning is "Setting property "IOSTANDARD' is not allowed for GT Terminals and this error is flagging only a single line in the constraint file yet ALL of the switches in the constraint file all do a "set_property IOSTANDARD LVCM0S33......... The final 2 critical warnings are "Cannot set LOC property of ports. Site location is not valid. This error is flagging two of the LED settings in the contraint file yet, once again, all 16 of the LED's are using the same commands within the constraint file. I'm at a brick wall trying to figure out what the heck the problem is here. As I said...the 1st Tutorial went fine. This tutorial even included the constraint file needed for the project. I've attached a zip file containing the entire Vivado project. Any help/advice would be greatly appreciated. THANKS! project_2.zip
  21. Hello, I am designing a project in which I need to register the input from a 4x4 matrix KeyPad (this model) and to do so I have written the following VHDL test code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Display is Port ( selected : in std_logic; Row_Vector : in std_logic_vector(3 downto 0); Col_Vector : in std_logic_vector(3 downto 0); display_code : out std_logic_vector(6 downto 0); display_ctrl : out std_logic_vector(3 downto 0) ); end Display; architecture Behavioral of Display is signal Displayed : std_logic_vector(3 downto 0); begin process(Displayed) begin case Displayed is when "0000" => display_code <= "0000001"; -- "0" when "0001" => display_code <= "1001111"; -- "1" when "0010" => display_code <= "0010010"; -- "2" when "0011" => display_code <= "0000110"; -- "3" when "0100" => display_code <= "1001100"; -- "4" when "0101" => display_code <= "0100100"; -- "5" when "0110" => display_code <= "0100000"; -- "6" when "0111" => display_code <= "0001111"; -- "7" when "1000" => display_code <= "0000000"; -- "8" when "1001" => display_code <= "0000100"; -- "9" when "1010" => display_code <= "0000010"; -- a when "1011" => display_code <= "1100000"; -- b when "1100" => display_code <= "0110001"; -- C when "1101" => display_code <= "1000010"; -- d when "1110" => display_code <= "0110000"; -- E when "1111" => display_code <= "0111000"; -- F when others => display_code <= "1111111"; end case; end process; process(selected,Row_Vector,Col_Vector) begin if selected = '0' then Displayed <= Row_Vector; else Displayed <= Col_Vector; end if; end process; display_ctrl <= "1110"; end Behavioral; I have attached all the source code for my test, which includes a button debouncer (U18 button), which I push to show the value that I read from the A14,A16,B15 and B16 pins for the rows and A15,A17,C15 and C16 for the columns of the KeyPad. For example: when there are no cables connected to the row pins and I have not pushed the button, the value read from the row pins is shown in the 7-Segment display, which is "1111" (F). This means that when I connect a cable on any of the pins, a '0' is written at the input pin. If I connect a cable at the first row pin, the value read is "1110" and E is displayed. Following this logic, when I connect a cable to the second row pin and I leave the other ones disconnected, it should be displayed D ("1101") but instead 8 is displayed, which corresponds to "1000", which would mean that I have row 1, row 2 and row 3 cables connected, which is not the case. What could be the problem here? My main problem is to undestand how to communicate the keypad with the Basys3 FPGA Test_Code.zip
  22. When I try to program my board after I generated the .bit/.bin files, i get the following error [Labtoolstcl 44-26] No hardware targets exist on the server [TCP:localhost:3121]Check to make sure the cable targets connected to this machine are properly connectedand powered up, then use the disconnect_hw_server and connect_hw_server commandsto re-register the hardware targets.it says no hardware exists on the server, even though my board is plugged in with the mode jumper in the JTAG position. I also tried reinstalling Vivado to make sure the cable drivers were installed.
  23. Hello everyone , I'm realtively new in programming FPGA's and needed some help . My micro-usb port got shorted so i had to resort to programming my basys-3 with a usb drive . I followed the reference file from digilent on that and everything was working fine . I used it the same way for the next few months . I stopped using the board for a months after and when i tried programming it today again , the bit file did got programmed . INstead the busy led next to the port forever keeps blinking . I tried formatting with FAT32 , resetting , testing the demo file on QSPI but nothing works even after all that . Like i said i'm very new to fpga's and mosty just implement basic codes to learn so i'm clueless when it comes to the next step . Any help would be apppreciated . Thank you . Regards, Supriya
  24. Hi! We are working with a Basys-3 FPGA and were wondering if it is possible to read large data files from a USB stick. We are trying to let the Basys 3 produce music through a module, but the internal ROM/Flash storage of the Basys is too small for, for instance, .Wav files or .Wav converted to .coe files. Is there a possibility to use the USB stick support for programming for this application or perhaps another method? Thanks! Kind regards, Jonathan
  25. Hello, I am trying to interface MCP3008 with basys 3 using SPI and store the values in a FIFO and transmit the values to PC using UART. Initially, I designed for ADC to convert input waveform and display results by increment or decrements of LED's. The MCP3008 ADC clock is 1.3 MHz clock. This works and led's increment as the amplitude of the input waveform is increased from signal generator . But when i receive through UART and plot on SerialPlot , the signal is distorted please find the code for ADC below: entity ADC is port ( -- command input clock : in std_logic; -- 100MHz onboard oscillator trigger : in std_logic; -- assert to sample ADC diffn : in std_logic; -- single/differential inputs channel : in std_logic_vector(2 downto 0); -- channel to sample -- data output Dout : out std_logic_vector(14 downto 0); -- data from ADC OutVal : out std_logic; -- pulsed when data sampled -- ADC connection adc_miso : in std_logic; -- ADC SPI MISO adc_mosi : out std_logic; -- ADC SPI MOSI adc_cs : out std_logic; -- ADC SPI CHIP SELECT adc_clk : out std_logic -- ADC SPI CLOCK ); end ADC; architecture behavioural ofADC is -- clock signal adc_clock : std_logic := '0'; -- command signal trigger_flag : std_logic := '0'; signal sgl_diff_reg : std_logic; signal channel_reg : std_logic_vector(2 downto 0) := (others => '0'); signal done : std_logic := '0'; signal done_prev : std_logic := '0'; -- output registers signal val : std_logic := '0'; signal D : std_logic_vector(9 downto 0) := (others => '0'); -- state control signal state : std_logic := '0'; signal spi_count : unsigned(4 downto 0) := (others => '0'); signal Q : std_logic_vector(9 downto 0) := (others => '0'); begin -- clock divider -- input clock: 100Mhz --100MHz/1.3MHz = 74/2 -- adc clock: 1.3MHz clock_divider : process(clock) variable cnt : integer := 0; begin if rising_edge(clock) then cnt := cnt + 1; if cnt = 37 then cnt := 0; adc_clock <= not adc_clock; end if; end if; end process; -- produce trigger flag trigger_cdc : process(adc_clock) begin if rising_edge(adc_clock) then if trigger = '1' and state = '0' then sgl_diff_reg <= diffn; channel_reg <= channel; trigger_flag <= '1'; elsif state = '1' then trigger_flag <= '0'; end if; end if; end process; adc_clk <= adc_clock; adc_cs <= not state; -- SPI state machine (falling edge) adc_sm : process(adc_clock) begin if adc_clock'event and adc_clock = '0' then if state = '0' then done <= '0'; if trigger_flag = '1' then state <= '1'; else state <= '0'; end if; else if spi_count = "10000" then spi_count <= (others => '0'); state <= '0'; done <= '1'; else spi_count <= spi_count + 1; state <= '1'; end if; end if; end if; end process; -- Register sample outreg : process(adc_clock) begin if rising_edge(adc_clock) then done_prev <= done; if done_prev = '0' and done = '1' then D <= Q; Val <= '1'; else Val <= '0'; end if; end if; end process; -- LED outputs PROCESS (adc_clock) BEGIN IF (adc_clock'EVENT AND adc_clock = '1') THEN CASE D(9 DOWNTO 6) IS WHEN "0001" => Dout <= "000000000000011"; WHEN "0010" => Dout <= "000000000000111"; WHEN "0011" => Dout<= "000000000001111"; WHEN "0100" => Dout <= "000000000011111"; WHEN "0101" => Dout <= "000000000111111"; WHEN "0110" => Dout <= "000000001111111"; WHEN "0111" => Dout <= "000000011111111"; WHEN "1000" => Dout <= "000000111111111"; WHEN "1001" => Dout <= "000001111111111"; WHEN "1010" => Dout <= "000011111111111"; WHEN "1011" => Dout <= "000111111111111"; WHEN "1100" => Dout <= "001111111111111"; WHEN "1101" => Dout <= "011111111111111"; WHEN "1110" => Dout <= "111111111111111"; WHEN "1111" => Dout <= "111111111111111"; WHEN OTHERS => Dout <= "000000000000001"; END CASE; END IF; -- END IF; END PROCESS; OutVal <= Val; -- MISO shift register (rising edge) shift_in : process(adc_clock) begin if adc_clock'event and adc_clock = '1' then if state = '1' then Q(0) <= adc_miso; Q(9 downto 1) <= Q(8 downto 0); end if; end if; end process; -- Decode MOSI output shift_out : process(state, spi_count, sgl_diff_reg, channel_reg) begin if state = '1' then case spi_count is when "00000" => adc_mosi <= '1'; -- start bit when "00001" => adc_mosi <= sgl_diff_reg; when "00010" => adc_mosi <= channel_reg(2); when "00011" => adc_mosi <= channel_reg(1); when "00100" => adc_mosi <= channel_reg(0); when others => adc_mosi <= '0'; end case; else adc_mosi <= '0'; end if; end process; end behavioural; --much of the code is of credit to micronova electronics. For fifo, I use the Xilinx IP fifo generator with no FWFT working on 100Mhz clock both on write and read sides. FIFO width = 10 Depth = 2046 and tried increasing upto 131072 with no progress. This is my top level code with UART entity top_module is Generic ( PARITY_BIT : string := "none" -- type of parity ); port( clk, rst,trigger,diffn: in std_logic; adc_mosi,adc_clk,adc_cs : out std_logic; adc_miso : in std_logic; channel : in std_logic_vector ( 2 downto 0); wr_uart,uart_clk_en : in std_logic; WriteEn , ReadEn : in std_logic; full, empty : out std_logic; --w_data: in std_logic_vector(7 downto 0); Dout : inout std_logic_vector(9 downto 0); busy : out std_logic; tx,OutVal: out std_logic ); end top_module; architecture structural of top_module is signal fifo_data_out : STD_LOGIC_VECTOR (9 downto 0); component fifo is port ( reset_rtl_0 : in STD_LOGIC; clk_100MHz : in STD_LOGIC; full_0 : out STD_LOGIC; din_0 : in STD_LOGIC_VECTOR ( 9 downto 0 ); wr_en_0 : in STD_LOGIC; empty_0 : out STD_LOGIC; dout_0 : out STD_LOGIC_VECTOR ( 9 downto 0 ); rd_en_0 : in STD_LOGIC ); end component fifo; begin MercuryADC : entity work.ADC port map ( clock => clk, trigger => trigger, diffn => diffn, channel => channel, -- data output Dout => Dout, OutVal => Outval, -- ADC connection adc_miso => adc_miso, adc_mosi => adc_mosi, adc_cs => adc_cs, adc_clk =>adc_clk ); fifo_i: component fifo port map ( clk_100MHz => clk, din_0(9 downto 0) => Dout(9 downto 0), dout_0(9 downto 0) => fifo_data_out(9 downto 0), empty_0 => empty, full_0 => full, rd_en_0 => ReadEn, reset_rtl_0 => rst, wr_en_0 => WriteEn ); uart_trx : entity work.UART_TX Port map ( CLK => clk, -- system clock RST => rst, -- high active synchronous reset -- UART INTERFACE UART_CLK_EN => uart_clk_en, -- oversampling (16x) UART clock enable UART_TXD => tx, -- serial transmit data -- USER DATA INPUT INTERFACE DATA_IN =>fifo_data_out (9 downto 2) , -- input data DATA_SEND => wr_uart,-- when DATA_SEND = 1, input data are valid and will be transmit BUSY => busy -- when BUSY = 1, transmitter is busy and you must not set DATA_SEND to 1 ); end structural; PFA the schematic of my design and waveform as well. input is 650 hz and Vpp= 1.5V; continuous sine wave. My output waveform appears to be distorted. I'm not sure if there has to be a delay incorporated while sampling the input signal or a is the issue between FIFO and UART. When WriteEn signal is asserted on FIFO, the full flag is asserted at the same instant, does that mean the size of FIFO is not enough. Kindly help, any inputs will be appreciated. MCP3008(3).pdf