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  1. Hello I am creating a verilog module on the basys 3 board to interface with the Pmod DA3. I have tried running the module with the DA3 connected and wasn't getting any voltage reading. I have my sclk speed at 25Mhz. Below is my current code and screenshots of my test bench and the pmod outputs on an oscilloscope. Any help is appreciated. `timescale 1ns / 1ps module sclk( input clock, input reset, output sclk ); reg[24:0] count = 0; reg sclk = 0; always @ (posedge clock or posedge reset) begin if (reset ==1'b1)begin count <
  2. I'm learning how to generate clocks with XDC files, using the .xdc from the Basys 3 github repository as a starting point. I'd like to change the clock to a very low frequency of 1 Hz, or once per second, so that a LED blinks on and off once a second. The portion of the .xdc file that generates the clock looks like this: ## Clock signal set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name sys_clk_pin -period 1000000000.00 [get_ports clk] And the code for blinking the LED looks like this: module oneclock (
  3. Hi! I've been playing with the low cost ESP8266 modules, that present a IP-over-WiFi as a serial device, and you use modem-like AT commands to control it. I've just put up a project that allows the FPGA to connect to my Wifi network, then send status message to a service that is listening on my Linux VM. It is all done using VHDL state machines (no software CPU), and could most probably be made a little more compact. Because the serial port is running at 9600 and the AT command based protocol overhead it is a pretty low bandwidth solution, but enough if you wanted to add some
  4. I tried to do this Pong game project https://github.com/CynicalApe/BASYS3-PONG and connect VGA to monitor. But monitor keeps flashing. Video im not sure if this problem appear because i have connected Basys3-> VGA adapter to hdmi -> wire hdmi to mini hdmi. Because my screen has only mini hdmi port.
  5. I am having layers of problems with the Pmod MicroSD. My ultimate goal is to get through the wifi example on youtube with a Basys 3. Today I am just trying to do the "hello world" demo for the micro SD Pmod. Issues: [Common 17-69] Command failed: BOARD_PART_PIN cannot be assigned to more than one port ["f:/microSD.srcs/sources_1/bd/microSD_bd/ip/microSD_bd_PmodSD_0_0/microSD_bd_PmodSD_0_0_board.xdc":7] I get this error for 4 pins set_property BOARD_PIN {JB7} [get_ports Pmod_out_pin7_t] set_property BOARD_PIN {JB8} [get_ports Pmod_out_pin8_t] set_property BOAR
  6. Hello I am attempting to follow this but I am confused about section 2.3. It says to place all the application code in DDR. The Basys3 has no external memory but for the SPI flash. From a SPI flash description from an Arty reference, it says but when I read the Xilinx answer record 63605, it says on step 5. Create helloworld application and link to DDR (in the linker script make sure that this application is executing from DDR) Can someone explain to me how to do this all in the SPI flash? Do I need to somehow set that up in my block design in? I do have the QSPI in my blo
  7. Tells me PmodWIFI is packaged with board value arty and to update my basys3 to the arty. I am confused. Well hang on a second. It finished generating a bitstream and I see no critical warnings in the project summary. In fact if I tell vivado to discard user generated messages in the messages window, the project has no indication of critical warnings at all. Still confused but closer to my goal.
  8. Hi there, I connected my Basys3 into my Ubuntu however no led turned on and my computer does not recognizes any device connected to it. Therefore, I'm afraid my FPGA has burned out or my USB-B connector is malfunctioning. Is it possible to change my USB-B part for a new one? Does Digilent provide any support for this kind of situation? Or will I have to buy another Basys 3? PS: I have already tried to connect it with a different cable, connect directly to a USB port in another computer as well, and none of these worked. Best regards, Igor Lima.
  9. I am completly new for the FPGA and basys3 development board. I have a project for Counter on the 7 segment displays on the board. We got 3 different layers as a design. cntr cntr_rtl cntr_top cntr_top_struc io_ctrl io_ctrl_rtl And in the project it has to diplay on the 7 segment controlled by the switches : count up / count down / hold / reset options: The priorities for these switches are: 1. reset 2. hold 3. count direction top level VHDL file cntr_top.vhd Port Name Direction Description clk_i In System clo
  10. Hello, I just bought 35 BASY3 FPGA boards for our Digital Systems class and need to install Vivado Design Suite in 30 computers. However I noticed during the installation process a window prompts on the "Select Installation Type" I have to enter USER ID and PASSWORD. I would like to know if there is a way around to having to create 30 accounts in order to install on 30 computers. I suppose I can try to install using 1 account on all 30 computers. Please help me with the best way to install Vivado Design Suite for my class. Thank you, Marco
  11. It is possible to program the Basys3 to be used as a motherboard diagnostics card ?
  12. Hello, Merry Christmas hope you guys are doing great. I am a beginner in digital design course and i want to implement this xadc demo project from digilentinc reference on my Basys3 FPGA. I'm having problems on the step 4 which is running the project as i can't figure the physical connections to connect to the JAXDC port on FPGA. Can someone confirm if the connections i have done in this picture are right? One last question. When you open the XADC Basys3 Demo project and see its constraints, only package pins i don't understand are these A12,B13 ones. Where a
  13. I'm still relatively new to Verilog and FPGA programming, so I've been struggling quite a bit with this one. The goal of the project here is to play a super basic game of 'blackjack' and I can't quite seem to get the system to work. As a note: The game goal is to get to 21, but a number reasonably high and close to 21 could still win the game based on what the Dealer has. The first few if - else if statements are there to interpret the card input from switches on the basys3, and then decide how much to add to the count based on the 'card' input. The latter if - else statement is there to
  14. Hello, I'm a student and currently working on my final project including Basys 3 board and wifi pmod. I'm trying to get started working with the module to understand how it works. This is my first project working with Pmods. I've been using the Getting Started with Digilent Pmod IPs tutorials. I added the newest Vivado library including the PmodWifi IP and I bulit a block design with the MicroBlaze and other GPIO IPs. I followed the instructions of the tutorials and got to the part of validating the design, there I got a warning saying few of the wifi pmod pin are not conne
  15. Hello, I new on Basys 3, and I need some examples for programming FPGA. In the resource center there are a lot of them, but the examples are written in verilog. I am using VHDL, so the questión is: Is there the same examples like the resource center written in VHDL?
  16. I am learning how to operate an FPGA, and I have to input a signal (which in itself is the output of a discriminator), and analyze it through a Basys3 FPGA. Looking at the available ports on the board, I'm guessing that it could be done using the Pmod ports, but even after hours of googling and going through the manuals, I failed to know which data ports to use, and how to read the signal after I've input it through the board. I've got references to some boards, in which GPIO ports are explicitly labelled, but I don't see any such labeling on the Basys3. So, it'd be really helpful if someone c
  17. I am working in an DSP algorithm, I have generated the bitstream for that algorithm and dumped into FPGA basys 3 board (the output of the algorithm is of 16-bit wide and consists of 100 samples). Now, I need to view the waveform with the help of Waveforms software and analog discovery kit. So, how it can be done? Can anybody provide me some video or anyother material that can solve the problem. #So far information obtained# In the material "Basys 3™ FPGA Board Reference Manual Overview" page no. 18, since, my data is of 16-bit wide I have connected pmod pins JB1 to JB4 to analog dis
  18. I want to send 8 bit data from FPGA to PC, 9600 baudrate, 8 bit data, 1 start&stop bit, no parity. I did coded my Basys3 Fpga and connected to PC. By using Tera Term, wanted to see how it works out. But probably something big I'm missing out. I just wrote a transmitter code and somewhere I saw that some people used button&top modules too. Do I need them to see a 8-bit data's ASCII equivalent on my PC? How can I handle? library ieee; use ieee.std_logic_1164.all; entity rs232_omo is generic(clk_max:integer:=10400); --for baudrate port(
  19. Hi, I have been familiarizing myself with VHDL and FPGAs in general with the Digilent Basys3 board. Recently I have tried incorporating the Microblaze in to my design just to familiarize myself with it. I have created a simple block diagram where I connect a custom AXI-stream counter to an AXI-DMA block. The counter just streams incrementing numbers and adds the tlast signal to generate frames. My purpose is to develop a minimum working example on AXI-DMA transfer. I plan to transfer x-number of samples generated by the AXI-stream counter with the AXI-DMA to a BRAM memory. On programming
  20. Hi, I am using Basys3 board and I want to write a RTL module in FPGA to get the character from USB Keyboard. From the Digilent reference of basys3, if the FPGA side only receive the data from Keyboard, then the PS_CLK and PS_DAT ports can be as input direction. My question is that, to receive the keycode from a keyboard, do we need to send configuration to Keyboard before hand ?
  21. Hello everybody, I am having a problem with the binary counter v12.0 reset SCLR signal, when implementing the Xilinx University Programme, Lab9 Project 3.1, 2015x (1). Environment: OS: Linux (Arch Linux) Xilinx Vivado 2018.3 Digilent Basys3 develoment board Verilog HDL Problem description: The project works as expected (counts up to 5 minutes, 0,1 second resolution), the exception is the counter reset button (BTNC, U18) is pressed it only stops the counting, when released, the counter is not reset, instead it keeps counting where it stopped. I am
  22. Hi all: I'm new to both Vivado and the Basys3 board. I've been working thru the initial tutorials to get myself familiar with the software and the board. The very 1st tutorial, Getting Started with Vivado, went fine. Everything worked as advertised. The problem I've run into is with the 2nd tutorial, Basys 3 Programming Guide Tutorial (https://reference.digilentinc.com/learn/programmable-logic/tutorials/basys-3-programming-guide/start). I have the latest version of Vivado (2018.3) and the tutorial was built with 2015.1. The tutorial even has a zip file to download both the s
  23. Hello, I am designing a project in which I need to register the input from a 4x4 matrix KeyPad (this model) and to do so I have written the following VHDL test code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Display is Port ( selected : in std_logic; Row_Vector : in std_logic_vector(3 downto 0); Col_Vector : in std_logic_vector(3 downto 0); display_code : out std_logic_vector(6 downto 0); display_ctrl : out std_logic_vector(3 downto 0) ); end Display; architecture Behavioral of
  24. When I try to program my board after I generated the .bit/.bin files, i get the following error [Labtoolstcl 44-26] No hardware targets exist on the server [TCP:localhost:3121]Check to make sure the cable targets connected to this machine are properly connectedand powered up, then use the disconnect_hw_server and connect_hw_server commandsto re-register the hardware targets.it says no hardware exists on the server, even though my board is plugged in with the mode jumper in the JTAG position. I also tried reinstalling Vivado to make sure the cable drivers were installed.
  25. Hello everyone , I'm realtively new in programming FPGA's and needed some help . My micro-usb port got shorted so i had to resort to programming my basys-3 with a usb drive . I followed the reference file from digilent on that and everything was working fine . I used it the same way for the next few months . I stopped using the board for a months after and when i tried programming it today again , the bit file did got programmed . INstead the busy led next to the port forever keeps blinking . I tried formatting with FAT32 , resetting , testing the demo file on QSPI but noth