Search the Community

Showing results for tags '@[email protected]'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Test and Measurement
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions


  • Community Calendar

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL







Found 7 results

  1. I had inserted FFT core in a design after FIFO .at the output i am expecting a frequency bin on certain index but i am not getting the result.FFT core is working on 100mhz clock . Following steps i had implemented . - For FIFO to be work on 100 MHz, I verified this by sending the captured data to MATLAB and analyze DATA over there. So I received data correctly. - I inserted FFT core after ADC_FIFO in the reference design. That FIFO working correctly on 100MHz clock. But I didn’t get the correct DATA from the core. For verifying FFT core settings,
  2. Hello, I am a student from Korea. I am trying to use a on board mic at nexys 4 ddr product. The final goal is to get noise level (such as 80dB). I have problems about understanding pdm modulation which is at page.24 of below pdf file. First of all, I thought I could get the noise level via couting each pdm signal occurs while a one clock pusle(if clock is 3Mhz timing will be 1/3 ns). But I'm not sure this is true. Even if it is true, I cannot find exact counting time to seek exact noise level. Can you help me with how to use on board mic as noise level? (via pdm modulation) I am usi
  3. Dear Sir, I am trying to generate Sinusoidal frequency using DDS Compiler in Vivado Block Designing and want to check its FFT Magnitude. I have few Querries to ask. First thing is that what will be the effect on output magnitude and xk_tuser index of FFT, if we use simple SINE or SINE AND COSINE. As in general we get two peaks for sine wave while for SINE AND COSINE we get single peak with added magnitude (please correct me if I am wrong). Secondly, I am not sure whether my FFT Magnitude Block is right or not (Figure Attached) , I have used two Slices at the output of FFT IP m_axi
  4. Dear Sir, I am trying to implement fir compiler in vivado block design. I have generated two frequencies , 200Khz and 1Mhz using DDS Compiler. I designed a Low Pass Filter Using FDATool in Matlab (figure attached). I am analyzing waveform using ILA but FIR Compiler output is either a straight DC or an irregular signal. I have attached Screenshots of block design, filter design and waveform. Your kind response will be highly appreciated.
  5. As we all know that pipelined processors has more latency and less execution time compared to non pipelined processors then why the latency of pipelined fft processors is less compared to radix-2 fft and radix-4 fft as per the xilinx fft ip latency of pipelined fft processor according to xilinx fft ip: 8341 cycles latency of radix-2 fft as per xilinx fft ip: 33009 cycles latency of radix-4 fft as per the xilinx fft ip: 14483 cycles below has the attachments of latency of different processors according to xilinx ip
  6. Hii, I had make a microblaze based AXILite ADC design which transfer data through Ethernet via TCP protocol. in SDK I have modified the echo server example code and transfer data frequently, till now everything works good, but when I am plotting this data using MATLAB tool ( ex. sine wave as input ) my real time graph for low frequency (upto 250 Hz) coming good but above this it became distorted and gives very unusual plot. I am attaching my plot and vivado design , please any one can suggest me what may be the reason for this or why I am getting like this output. pl
  7. fpga_123

    Nexys 4 DDR

    What would be the maximum amplitude of the signal that can be given to microphone present on nexys 4 ddr board ?