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Found 4 results

  1. I had inserted FFT core in a design after FIFO .at the output i am expecting a frequency bin on certain index but i am not getting the result.FFT core is working on 100mhz clock . Following steps i had implemented . - For FIFO to be work on 100 MHz, I verified this by sending the captured data to MATLAB and analyze DATA over there. So I received data correctly. - I inserted FFT core after ADC_FIFO in the reference design. That FIFO working correctly on 100MHz clock. But I didn’t get the correct DATA from the core. For verifying FFT core settings, I debugged FFT core with a DDS core. I mean generate a signal from DDS core and passed to FFT core, at the output I got correct result. So FFT core is also working fine s_axis_data_tdata[31:0] ( input [ real 16 bit , q 16 bit ] ) s_axis_data_tlast (I provide this signal from a counter which run upto FFT points) s_axis_data_tready [ output] s_axis_data_tvalid [coming from fifo] s_axis_config_tdata [ passed 0] s_axis_config_tready [ output] s_axis_config_tvalid [constant 1] m_axis_status_tready [constant 1] m_axis_data_tready [constant 1]
  2. As we all know that pipelined processors has more latency and less execution time compared to non pipelined processors then why the latency of pipelined fft processors is less compared to radix-2 fft and radix-4 fft as per the xilinx fft ip latency of pipelined fft processor according to xilinx fft ip: 8341 cycles latency of radix-2 fft as per xilinx fft ip: 33009 cycles latency of radix-4 fft as per the xilinx fft ip: 14483 cycles below has the attachments of latency of different processors according to xilinx ip https://www.xilinx.com/support/documentation/ip_documentation/xfft/v9_0/pg109-xfft.pdf page 41 to 43 has different block diagrams of fft processors.Do let me know please about latencies why pipelined fft processor has less latency and how to find throughput of it.
  3. Hii, I had make a microblaze based AXILite ADC design which transfer data through Ethernet via TCP protocol. in SDK I have modified the echo server example code and transfer data frequently, till now everything works good, but when I am plotting this data using MATLAB tool ( ex. sine wave as input ) my real time graph for low frequency (upto 250 Hz) coming good but above this it became distorted and gives very unusual plot. I am attaching my plot and vivado design , please any one can suggest me what may be the reason for this or why I am getting like this output. please suggest my mail ID IS : shubham.dwivedi@eiwave.com
  4. sgandhi

    Nexys 4 DDR

    What would be the maximum amplitude of the signal that can be given to microphone present on nexys 4 ddr board ?