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Showing results for tags '8x1 multiplexer'.
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Hello, I want to design 8x1 multiplexer using FPGA. But, I just only have 5 options of input, which are freq1, freq2, freq3, freq4, and freq5. Is it possible to design it with only just have 5 options of input? If possible, how doing it? I'm using Xilinx and the language I used is VHDL. Here I attach a picture. Please help me. Thank you.