Search the Community
Showing results for tags '7segment'.
Found 5 results
-
Hello, (FPGA board is Nexys A7 100T) So my end goal is to implement RC4 stream cipher and implement it onto FPGA. I was trying to configure a switch that will utilize the 7-segment 8- digital display and display my original plain text. And another switch that will display the encrypted text. I have attached the sources and test benches below that works. And have screen captured the simulation to show the results. Thanks for spending the time, I'll be high alert for response and try to respond on follow up questions. Can someone help me with this?
-
Hello, I found a lot of open source and tutorials on how to build a 4 digit 7 segment display on the Nexys A7 board (or Nexys 4DDR). I was wondering how can I make all 8 digital displays light up and display a message in hexadecimals (ex: "85ECA921"). I'm doing this in xlinx vivado in VHDL code. I'll have attached of something that works for 4 digits, but can someone show me how to implement/ change the code to make all 8 digital displays work in that example I provided? Thanks serializer.xpr tb_serializer.vhd serializer.vhd my_genpulse.vhd hex2sev
-
Hi, We can see two dots on 7 segment display which usually present second in clock configuration. However, their pins are not defined in constraints file. I don't have much hope cause it seems the display has 12 pins (8 digit, 4 display). Can we use those dots? If so which pins are they tied to? Thanks in advance. Bora
-
Hi, Ever since I programmed my Basys3 board via JTAG for the first time, I noticed that the 7-segment displays would stay slightly on despite not using them in my projects. Is this type of behavior to be expected? If not, does anyone know how to overcome this issue? Thank you.
-
I am able to program my Nexys 3 board but it seems like when I power cycle it the program is lost and it goes back to the pre-loaded configuration that says "pass" on the 7 segment display. I can then load the program again and it works. What is the expected behavior? Does the FPGA have to programmed every time it starts? Is this a jumper setting I need to change to get it to maintain its state after power cycle? Thanks.
