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Found 1 result

  1. Hello everyone, So I own a Basys 2 board with spartan 3E FPGA and I am using ISE Design Suite 14.5. I want to create a VGA output with 800x600 resolution and 40Mhz clock so it will have 60Hz refresh rate. I am writing the code in verilog. I have entered exact numbers for horizontal counter, vertical counter, hsync and vsync that are required for operation stated above. However, I am unable to output the VGA signal. I am using two DCMs that can be generated in the ISE design suite, I am using first DCM to multiply 50MHz clk to 100Mhz and then I am using second DCM to divide 100Mh