Search the Community

Showing results for tags '2017.2'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 2 results

  1. I have successfully used Vivado to store the bitstream into flash. On power-up, however, it does not program itself. If I push the PROG button, it does load the program from flash. That takes about 6 seconds. Two questions: 1. how do I get the program to auto-load? 2. how can I get it to load faster? the default program from Digilent loads in under a second. Thanks!
  2. Hi, I am running through the Creating a Custom IP core using the IP Integrator tutorial using Vivado 2017.2 and have run into a number of problems as follows. In section 4.1) Adding the the line, parameter integer PWM_COUNTER_MAX = 1024, Causes Vivado to mark the line with the warning, Warning: syntax error near "Integer". In section 4.2) Adding the lines, output wire PWM0, output wire PWM1, output wire PWM2, output wire PWM3, Causes Vivado to mark the first line with the warning, Warning: syntax error near "wire". In section 4.3) Adding the line, reg [15:0] counter = 0; Causes Vivado to mark the first line with the warning, Warning: syntax error near "15". Adding the remainder of this section causes a number of errors reporting that has not been declared. I have attached the VHDL file that I am working on. Any ideas why I am getting these issues? Forgive me as my VHDL is not very good at the moment and the issues I am having are probably only minor. Regards FarmerJo my_pwm_core_v1_0_S00_AXI.vhd