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Showing results for tags 'zynq7'.
Hi, I have a MYIR Z-turn board with a Zc-7020 SoC. Recently, I bought an HS3 programming cable, however for some reason, I cannot get the HS3 to communicate with the Zynq7. I am using Vivado 2017.4. I already use the DLC9 programming cable and it is able to programme the PL part of the SoC however, I need the 100MHz clock to run and there is no documentation that show how to start the PS part using the DLC9 programming cable - that is why I bought the HS3 cable. Can anyone help please?
Hello, I have recently purchased Zedboard along with Pmods AD1 and DA4. I want to implement Gradient Descent algorithm in the Zedboard using these Pmods with bandwidth more than 100 kHz. To get started, I tried to regenerate a analog signal using the Pmods AD1 and DA4. The experiment is completely explained with block design and output plots in the ADC_DAC_1_compressed.pdf. The SDK C code for acquistion and generation (adc_dac.c) as well as for finding max. working speed of DAC (dac_maxv.c) are atttached. The ADC clk is set to 20 MHz and DAC clk is to 50 MHz. It could be observed fro
Hi, I'm trying to make PmodAD5 work with a Zedboard by using Vivado 2016.2 (can also use earlier versions if needed). Digilent has a nice wiki pages to use Pmods with Zedboard, especially for using Pmod IPs: https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips/start In this tutorial, however, there is no PmodAD5, and there reference design linked from Digilent product page to AD also has the implementation example for Xilinx ISE 14.4: https://wiki.analog.com/resources/fpga/xilinx/pmod/ad7193 Nevertheless I tried to combine the information I cou