Search the Community

Showing results for tags 'zynq'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments and the WaveForms software
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 113 results

  1. Hi, I wanted to know if there are any official plans to support the Python Productivity for Zynq - PYNQ packages for Arty Arty Z7-10 or Arty Z7-20. Since there are very likely going to be overlaps in their target audiences, hobbyists and new learners. It would be awesome for Arty Z7-x to be an officially supported platform.
  2. I recently purchased the Zybo, zynq development board, along with a MIC3 so that I could hopefully take in audio from the PMOD port and then process it in Arm processor, and finally output it through the audio output port. I'm having trouble getting the audio routed with the IP in vivado. I'm fairly new to the vivado IP integrator but I have some experience creating verilog projects. Has anyone used the MIC3 with the zybo, or know how to get the audio from a MIC3 in one of the PMOD ports, into the ARM for proccessing? Any help would be greatly appreciated.
  3. Hi guys, I bought a zybo board and did a simple hello world project to test the functionality, but it didn't work. Here's what I've done: After exporting hardware and creating sdk projects, I downloaded the bitstream & program into zybo as usual. But the board wouldn't run the program normally(It doesn't terminate and doesn't print helloworld). So I debug the board using xsdb, step by step, and find out that disassembly result is not the same as elf file displayed in SDK. xsd shows that data at 0x100000 is 0xea020049; however, in the sdk, the data should be 0xea000049, as shown in the second picture. If I keep on stpi, since it'll go to the wrong place, CPU will finally goto infinite loop. xsdb% connect tcfchan#0 xsdb% targets 1 APU 2 ARM Cortex-A9 MPCore #0 (Running) 3 ARM Cortex-A9 MPCore #1 (Running) 4 xc7z010 xsdb% fpga -f "design_1_wrapper_hw_platform_0/design_1_wrapper.bit" 100% 1MB 1.8MB/s 00:01 xsdb% targets 2 xsdb% source "design_1_wrapper_hw_platform_0/ps7_init.tcl" xsdb% rst; ps7_init; ps7_post_config; Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0xffffff28 (Suspended) Info: ARM Cortex-A9 MPCore #1 (target 3) Stopped at 0xffffff34 (Suspended) xsdb% dow "hello_world/Debug/hello_world.elf" Downloading Program -- C:/Xilinx/Zybo/project_2/project_2.sdk/hello_world/Debug/hello_world.elf section, .text: 0x00100000 - 0x001016eb section, .init: 0x001016ec - 0x00101703 section, .fini: 0x00101704 - 0x0010171b section, .rodata: 0x0010171c - 0x00101733 section, .data: 0x00101738 - 0x00101bab section, .eh_frame: 0x00101bac - 0x00101baf section, .mmu_tbl: 0x00104000 - 0x00107fff section, .init_array: 0x00108000 - 0x00108003 section, .fini_array: 0x00108004 - 0x00108007 section, .bss: 0x00108008 - 0x0010802f section, .heap: 0x00108030 - 0x0010a02f section, .stack: 0x0010a030 - 0x0010d82f 100% 0MB 0.4MB/s 00:00 Setting PC to Program Start Address 0x00100000 Successfully downloaded C:/Xilinx/Zybo/project_2/project_2.sdk/hello_world/Debug/hello_world.elf xsdb% mrd 0x100000 16 100000: EA020049 100004: EA040025 100008: EA00002B 10000C: EA00003B 100010: EA000032 100014: E320F000 100018: EA000000 10001C: EA00000F 100020: F92DD91F 100024: ED3F1FBB 100028: ED6D0B20 10002C: EEF11A10 100030: 00001004 100034: 00001A10 100038: FFFF1004 10003C: EFF1019E elf file contents: Disassembly of section .text: 00100000 <_vector_table>: 100000: ea000049 b 10012c <_boot> 100004: ea000025 b 1000a0 <Undefined> 100008: ea00002b b 1000bc <SVCHandler> 10000c: ea00003b b 100100 <PrefetchAbortHandler> 100010: ea000032 b 1000e0 <DataAbortHandler> 100014: e320f000 nop {0} 100018: ea000000 b 100020 <IRQHandler> 10001c: ea00000f b 100060 <FIQHandler> 00100020 <IRQHandler>: 100020: e92d500f push {r0, r1, r2, r3, ip, lr} 100024: ed2d0b10 vpush {d0-d7} 100028: ed6d0b20 vpush {d16-d31} 10002c: eef11a10 vmrs r1, fpscr 100030: e52d1004 push {r1} ; (str r1, [sp, #-4]!) 100034: eef81a10 vmrs r1, fpexc 100038: e52d1004 push {r1} ; (str r1, [sp, #-4]!) 10003c: eb00019e bl 1006bc <IRQInterrupt> So, the problem is, WHY is the DRAM data partially wrong??? I almost doubt DRAM works normally, but I just bought the board a week ago lol.
  4. Recently I had to make a standalone Zynq project that had multiple .ELF files all residing on an SD card. The board had to somehow know, while being powered off, which .ELF file to boot from. So how to do this? The answer is in the FSBL file. Currently, in Vivado's 2014.2 SDK, the FSBL can handle multiple "partitions" (that's how any Second Stage BootLoader is called, in our case the .ELF files) by executing the first one, when done returning to the FSBL that handoffs control to the second one and so on. But there is another way with the so called hooks: FsblHookBeforeBitstreamDload, FsblHookAfterBitstreamDload, FsblHookBeforeHandoff. With these handy functions you can halt the FSBL and do whatever (for example read the switches) before the bitstream file has been downloaded, after or right before the SSBL is being booted. Here's a simple usage example: let's you have three .ELF files on the SD card and you want to select which one to boot with the on-board switches. First of all you generate an FSBL project, then open the image_mover.c file from the src folder. Scroll down to line 440 and change the code as bellow: if (PLPartitionFlag) { if (PartitionAttr & ATTRIBUTE_PS_IMAGE_MASK) { Status = FsblHookBeforeBitstreamDload(); if (Status != XST_SUCCESS) { fsbl_printf(DEBUG_GENERAL,"FSBL_BEFORE_BSTREAM_HOOK_FAILrn"); OutputStatus(FSBL_BEFORE_BSTREAM_HOOK_FAIL); FsblFallback(); } else { HeaderPtr = &PartitionHeader[ExecutionAddress]; PartitionDataLength = HeaderPtr->DataWordLen; PartitionImageLength = HeaderPtr->ImageWordLen; PartitionExecAddr = HeaderPtr->ExecAddr; PartitionAttr = HeaderPtr->PartitionAttr; PartitionLoadAddr = HeaderPtr->LoadAddr; PartitionChecksumOffset = HeaderPtr->CheckSumOffset; PartitionStartAddr = HeaderPtr->PartitionStart; PartitionTotalSize = HeaderPtr->PartitionWordLen; ExecAddress = PartitionExecAddr; } } } Open the fsbl_hooks.c file and add the following global variable: extern u32 ExecutionAddress; Go to the FsblHookBeforeBitstreamDload function and change it: u32 FsblHookBeforeBitstreamDload(void) { u32 Status; u32 dwSws; Status = XST_SUCCESS; // The first partition would usually be the PL bitstream, so we're // skipping it. do { dwSws= Xil_In32(SWS_BASEADDRESS) & 0x03; } while(dwSws == 0x00); ExecutionAddress = dwSws; xil_printf("Selected partition %drn", swSws); /* * User logic to be added here. Errors to be stored in the status variable * and returned */ fsbl_printf(DEBUG_INFO,"In FsblHookBeforeBitstreamDload function rn"); return (Status); } ExecutionAddress will hold the value of the first two switches and point to the corresponding partition. And finally here's how the "Create Zynq Boot Image" SDK utility would look like when creating the BOOT.BIN that'll go onto the SD: That's it! Hope it helps someone (or even myself sometime in the future when I forget all this ).
  5. I am trying to create an interrupt handler using Zynq. I am using the Zybo board and am using the Linux kernel from the following link: https://github.com/Xilinx/linux-xlnx.git. I have searched the Internet and I think I have everything set up properly but my handler never gets called in my driver. Here is my block design: ... and my interrupts set up in vivado: My dts file (attached here) contains the following: ps7_gpio_0: [email protected] { #gpio-cells = <2>; clocks = <&clkc 42>; compatible = "xlnx,zynq-gpio-1.0"; emio-gpio-width = <64>; gpio-controller ; gpio-mask-high = <0xc0000>; gpio-mask-low = <0xfe81>; interrupt-parent = <&ps7_scugic_0>; interrupts = <0 59 4>; reg = <0xe000a000 0x1000>; } ; I am trying to hook interrupt 91 on the PS that is triggered from PL using AXI GPIO. I have subtracted 32 from 91 hence the <0 59 4> in the dts file. My interrupt_v1_0 IP simply creates a 10ns pulse every second. I expect to see my interrupt function being called in the driver every second once I load my bitstream and driver but this does not happen. Can someone please check and tell me what I am doing wrong? I have attached my driver, dts and code for my interrupt IP here. Thanks. zynq-zybo.dts interrupt.vhd driver.c
  6. I am walking through the Getting Started With Zynq tutorial and am at a crossroads in the design. In step 5.2) of the tutorial: "After the design validation step we will proceed with creating a HDL System Wrapper. In the block design window, under the Design Sources tab, right-click on the block diagram file. We labeled it “design_1.bd” and select Create HDL Wrapper." Vivado gives me a pop up with two options and the tutorial doesn't provide any guidance. If I were not so new to FPGA design maybe the answer would be clear as day but as a beginner I wish these detail were more clear. Copy generated wrapper to allow user edits Let VIvado manage wrapper and auto-update The window also states;"You can either add or copy the HDL wrapper file to the project. Use copy option if you would like to modify this file." The next step moves on to generate a bitstream file so I'm going to assume that this file will not be edited any longer. I wish the tutorial would provide a bit more context to the steps laid out and how the operations used in this simple project would/could be used in another project. So far I appears that once I'm done this this tutorial I will only have learned how to accomplish the same task, only with a bit more confidence. After step 6 I am given another window the tutorial does not make any mention of. The window is titled Launch Runs with text; "Launch the selected synthesis or implementation runs." and provides 3 choices. Launch runs on local host: Generate scrips only Number of jobs [2] {with option to change value} There is also a choice of Launch directory. On this one I'm totally clueless. I realize that Diligent is not responsible for changes in the Vivado IDE but I as a company focused on education I think it could do better on updating tutorials to accurately reflect the changes in Vivado. I would also LOVE to see more Zybo tutorials, they are far and few between on the net. The book is alright but a bit difficult to navigate to topics the relevant for beginners. If anyone could respond with instruction on how I SHOULD have proceed with these options and what any of these options really mean I would appreciate it, as I have now come across some warnings in the TCL console about needing a "AXI BFM license to run".
  7. I am attempting to sample values from the XADC and use those values to control a video display connected via VGA. Both of these parts work separately, but when I attempt to combine the hardware for the two, the XADC stops working. Specifically, the XADC still returns values, and those values still fluctuate slightly, but they don't represent the voltage anymore. I'm using the XADC in single channel mode, and have tried both channels 6 and 14. I've connected my analog input to PMOD-JA in the appropriate places for channel 6 and 14. Both of these channels function perfectly in my XADC only design, but when I add the VGA display hardware they stop working. The values returned by the XADC still fluctuate, so it's sampling something, just not the thing I want it to sample. For example, I had a voltage difference of approximately 0.37 volts across channel 14 and some of the 16-bit values returned by the XADC were 206, 187, 196, 226, 201, 220, 201, 187, 222, 229, 192, 213, and 225. These values stay in this 100-200 range even if the voltage is changed. Again, the correct values are returned when using the hardware without the VGA display. Adding the VGA hardware breaks it. I'm interested to know if anyone has successfully used both the VGA output and the XADC in the same project, and if they had to do anything special to get the setup working. If necessary, I could provide code or a Vivado project that demonstrates my issue. Thanks!
  8. Hi every one, I'm trying to have My Smartphone (Sony Xperia Z2) MHL (TV-OUT) output in ZYBO HDMI input. When I use my laptop HDMI output (720p), the ZYBO works correctly, But when I connect My Smartphone via MHL(Mobile High-Definition Link) cable, Idon't have any output from VGA port. I must say that I tested phone MHL output on TV and it worked perfectly (1280*[email protected] & 1920*[email protected]). Please help me about this problem. Best regards. Sina shiri
  9. I'm trying to understand how to set up clocks and read data from a MIPI camera sensor. The sensor (Omnivision 5647) uses the MIPI CSI-2 protocol with D-PHY for the physical layer. The stage I am trying to get to is to be able to observer SoT (Start of Transmission) signals after which I can start parsing the CSI-2 protocol packets. In a small MIPI writeup located at http://archive.eetasia.com/www.eetasia.com/ART_8800715969_499489_TA_a466fca2_3.HTM there are 2 statements that are to be taken into consideration when trying to read data: "The high speed payload data from the transmitter is transmitted on both the edges of the High speed differential clock (DDR clock)" "The high speed differential clock and the data transmitted from the transmitter are 90 degrees out of phase and with the data being transmitted first." Using VHDL and Vivado, how do I create logic to successfully read data from this sensor? I have the following code written (with notes/questions) but I'm pretty sure its wrong. It was put together based on my limited understanding and reading various other source code that perform similarly: http://pastebin.com/FGvChHis I was told that in order to derive the correct delay value I would have to sample the output clock at the rising edge. If it is not 1, decrement the delay value. If it is 1, increment the delay value. This way the delay should always be within +/- 1 of the ideal value. I have experimented with this code and tried to see how many SoT's I can detect but its very low (<10 per minute). This is probably due to random chance. Really need help on this one!
  10. Hey there I'm thinking about purchasing a Zybo or Zedboard to Implement a SDR application. I'm in electronics engineering student with microcontroller history but brand new to FPGAs. I have a few questions about the vivado license, ISE vs Vivado for DSP applications. What exactly is it that the licence that Digilent sells offer that the webPack dosent? I have read here on the forums about some discrepancy between the Vado licenses and forgot it updates in this regard. Is the CihipScope offered in the wet pack now? I may later decide to purchase the SDR software package offered by AVNET, or at least individually accumulate those licenses as my budget allows. So how dose the webpack version limit my ability to integrate with the software elements(currently unable to find the said software package) used for SDR & DSP development? What are the limitations of the Pmod interface if I were to go with the Zybo and later try to coonect to a FMC interposer/Analog Devices ACD boards? Im reading the zybo book but any links to more learning resources would be greatly appreciated. I'm ready to pull the trigger on a purchase today as soon as I get these questions answered. Looked high and low for a phone number
  11. Hello, I am trying to program a new zedboard and am having trouble programming the ps portion of the board with a bare metal application. I am following the tutorial outlined in the zynq book, in which you load some pre-written c code, which should blink some leds. Unfortunately, I keep getting stuck on the programming of the board. I select run as -> Launch On Hardware and it gets about 89% of the way though the program and then hangs on "Launching: ps7_init". Has anyone seen this before? I have tried it on both Ubuntu 16.04 and Windows 10, and both give the same problem. Furthermore, I am able to run "connect arm hw" in XMD console and it appears to work fine. I am also able to program just the PL fine as well through Vivado or SDK. I also don't think it is my header pin settings? I have them all set to gnd, which should be boot from JTAG. Other Info: Operating System: Tried on both Windows 10 and Ubuntu 16.04 (Virtual Machine) Vivado/SDK Version: Tried on both 2016.2 and 2016.4 ZedBoard: Latest Rev (D?) Power Source: Provided wall plug into US 120v 60hz
  12. Hello, I've recently purchased a PYNQ-Z1 dev board and am working to follow the examples in the Adam's MicroZed Chronicles. I'm able to successfully create the reference design in Vivado consisting of only ZYNQ PS, generate bitstream, Export HW Design and also create software projects that run on the target device in the SDK via JTAG. When attempting to create the boot image and flash, I've been unable to get the anywhere via QSPI or by placing the .bin file directly on the SD card and using the SD boot option switch. Here are the steps I've taken thus far: Create new Vivado Design project referencing the Digilent Arty-Z7-20 Board Added the ZYNQ PS Connected M_AXI_GP0_ACLK to FCLK_CLK0 and fast foward....generated Bitstream Exported HW Design Create Sample Hello World Project in SDK (tested successfully and runs perfectly via JTAG) Generate FSBL Create Boot Image - Added elf bootloader from FSBL - Added bitstream from HW Export -- This generates the bin file used to program flash in the next step Program Flash - Selected the HW Platform Exported from Vivado - Used Image file created above - No Offset - Flash Type qspi_single Flash programming completes successfully. I select QSPI, power cycle the board and fail to get the done LED on the board indicating that the FPGA bitstream has been downloaded. I place the same bitfile named boot.bin on the SD card and get the same result. Nothing. Any suggestions? Is there some strange delta w/ the Digilent board I'm using that I don't know about. Additionally, the example bin file provided by Digilent works perfectly.
  13. Hi everyone, I have seen discussion on this topic already in previous posts, but I am hoping someone has made a little progress and just hasn't posted yet. I'm hoping to be able to play audio (SFX & music) in a pong game I've made with Zybo. Does anyone have tips/experience on how to achieve this? FYI: I have an SD card, so that would be an option for audio file storage. Thanks for your time and effort! I am enjoying Zybo immensely so far. -Josh
  14. I'm new to FPGAs and the zynq. I'm interested in a zybo board and would like to know how to put an lvds output on the logic part of the zynq and how to get this connected to a framebuffer device I can use in linux to output graphics to?
  15. Hi I will my first zybo program Hello World like this link https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq/start?redirect=1id=zybo:gsg But I cant chose zybo option because it isnt My secreen view is here: why there is not zybo option ?
  16. I trying to use clock capable pin U15 on the Zynq using a Zybo board. According to ug865-Zynq-7000-Pkg-Pinout.pdf U15 is one of the pins that are clock capable (MRCC/SRCC): However I am getting the "Poor placement for routing..." error suggesting that I use "CLOCK_DEDICATED_ROUTE FALSE" which states is undesirable. Any idea what is going on here? I'm trying to use this with a high speed camera interface. thx
  17. Professors and researchers from University of Houston make use of Zedboard and Xilinx Vivado High Level Synthesisto implement the data encryption in the cloud computing. They explained this concept in two different conferences Field Programmable Logic (FPL) 2014 - Privacy Preserving Large Scale DNA Read-mapping in MapReduce Framework using FPGAs http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6927414 IEEE Cloud 2014 - PFC: Privacy Preserving FPGA Cloud - a Case Study of MapReduce http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=6973752&url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel7%2F6968679%2F6973706%2F06973752.pdf%3Farnumber%3D6973752 The project is also sponsored by NATO. http://www.uh.edu/news-events/stories/2016/March/032316ShiNATO
  18. Hi every one. I was Created HLS Ip Core. This Core is a simple Image Filer, and the input for this Core is a matrix of picture that I built in Matlab, Now I'm trying to have a input from HDMI and filter output from VGA. In other words, I don't know "How create a simple block design in ZYBO for have HDMI input, VGA output and HLS IP CORE?" and "Which commands need to read frames from input in SDK sowftware?" Best regards. Abish SJ
  19. malkauns

    Zybo board 1.8V logic

    I have a quick question. I am trying to interface my Zybo board with a camera module (Arducam OV5640). The datasheet says that it uses 1.8/2.8V logic. In my XDC file do I simply use IOSTANDARD LVCMOS18 for each pin? I have tried this using the pmod connectors on the Zybo board and setting one pin high but when I check the voltage with a multimeter it reads 3.3V.
  20. Hello everyone; I am trying to boot Linux on Zybo using this tutorial: http://www.instructables.com/id/Embedded-Linux-Tutorial-Zybo/?ALLSTEPS I have load Boot,bin, devicetree.dtb uImage and uramdisk.image intor fat32 partition of my 16 Gb sd card. size of uramdisk.image is around 5 Mb. when I boot the Linux, I have the problem like this, BAD DATA CRC h Do you have any experience on that ? is the size of kernel correct?
  21. Abish sj

    BOOT IMAGE

    Hi guys, A screen shot as you see below is a SDK projects that has two system_wrapper_hw_platform folder. this program work properly when I program from JTAG, But when I'm trying to create BOOT Image, it's not work. How can I create the boot in this situation? please help me about this problem. thanks.
  22. Hardent release board support package file and design file of Petalinux for ZYBO. Check out their blog: http://www.hardent.com/electronic-FPGA-design-consulting-services/petalinux-zybo-bsp-now-available-to-download/
  23. Hello, How can I communicate with the SD card in bare metal application at Zybo board< There are some free FAT32/16 filesystem stacks, but how to make them work with Zybo HW? Is there any reference solution for file read/write?
  24. Takeways: 1. Maximize the usage of the Xilinx Zynq 7000 resources 2. Understand the nuances and internal workings of the Xilinx Zynq 7000 3. Trade-off performance vs. energy consumption Complexity of systems implemented using FPGA's are exponentially growing in a rapid pace. As a result of it most of the common design issues that a designer come across with ASIC SoC are becoming relevant with FPGA as well. If we consider Xilinx Zynq 7000 Programmable SoC, there is considerable processing power on the compute side. A simple migration is insufficient to achieve the same performance as discrete chips and also achieving performance and implementation benefits of such a complex FPGA would be very less. Estimating or identification of system performance and crucial bottlenecks much before writing RTL not just reduces the development time but also increases the Quality of Results. During this event we will be talking about how performance analysis and architecture exploration of a Zynq 7000 based System in the early stage of system development ensures that the right FPGA platform is selected and achieves optimal partitioning of the application onto the fabric. To Register, Click here
  25. Mehdim

    how to define constraint

    Hello guys; Can anyone help me how to assign a port to specific pin in Vivado? I am using custom port on AX_GPIO module and I want to add it to one of PMOD connectors; I am using this command to connect it to V12 set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { gpio2_io_o }]; it works fine, but if I want to assign a vector port to some pins(for example gpio2_io_o[7:0] ) what should I do to define constraint?