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  1. Hello to al, The system is built on the Zybo board in standalone mode. So far I had success sending interrupts from PL via GPIO. In order to reduce complexity I decided to try sending interrupts directly as it is shown on the included diagram. The RTL module is a simple counter sending a pulse once in a period of time. ILA confirmed the pulse. The application is supposed to count 50 interrupt events and quit. However, no triggering is happening. Clock freq is 50 MHz and a counter is 16 bit. The C-code is taken from two sources: Xilinx Timer-interrupt example and Avnet interrupt tutor
  2. Hello to everyone, I want to show the temperature data with Teraterm . I get from PMOD TMP3 . But I have to design the PMOD TMP3 IP and I do not know what is the difference with led_ip_design on the link there. https://forums.xilinx.com/xlnx/attachments/xlnx/gendis/16930/1/adding ip.pdf Can you help me? How can I show the temperature data?
  3. ihab.adly

    Zybo board

    I recently bought a board Zybo Zynq-7000 manufactured by your company and contains the Xilinx XC7Z010-1CLG400C chip. However, when I tried to get the free version of the Vivado to operate my board, I received the following message: "Failed Export Compliance Verification". I am now stuck with my board and cannot make any use of it. I am living in Egypt and there was no restriction whatsoever getting the board, so how come I am not able to get the necessary software to use it. Please advise.
  4. I just received my Arty Z7! I'm trying to get a basic example up and running. Since there aren't any tutorials up yet on the Arty Z7 start page: https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start so I tried to follow the "Getting Started with Zynq" example for the Zedboard: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zedboard-getting-started-with-zynq/start I created the project using the Arty Z7 20 Vivado board files. Everything went smoothly until I try run the code example (Launch on Hardware). I get: ERROR : Me
  5. Question to experts: What is the fastest way for saving continuous data coming from PL on Zynq without requiring the processor you would recommend? The data rate is expected to vary in the range 4-8 MB/s. Preferred processor operational mode is standalone. Options considered so far are BRAM, OCM and DDR3. All of these options seems require custom HDL coding to interface Zynq memory. Before comitting to such effort I'd like to hear opinions from the community. Thank you!
  6. Hi, I wanted to know if there are any official plans to support the Python Productivity for Zynq - PYNQ packages for Arty Arty Z7-10 or Arty Z7-20. Since there are very likely going to be overlaps in their target audiences, hobbyists and new learners. It would be awesome for Arty Z7-x to be an officially supported platform.
  7. I recently purchased the Zybo, zynq development board, along with a MIC3 so that I could hopefully take in audio from the PMOD port and then process it in Arm processor, and finally output it through the audio output port. I'm having trouble getting the audio routed with the IP in vivado. I'm fairly new to the vivado IP integrator but I have some experience creating verilog projects. Has anyone used the MIC3 with the zybo, or know how to get the audio from a MIC3 in one of the PMOD ports, into the ARM for proccessing? Any help would be greatly appreciated.
  8. Recently I had to make a standalone Zynq project that had multiple .ELF files all residing on an SD card. The board had to somehow know, while being powered off, which .ELF file to boot from. So how to do this? The answer is in the FSBL file. Currently, in Vivado's 2014.2 SDK, the FSBL can handle multiple "partitions" (that's how any Second Stage BootLoader is called, in our case the .ELF files) by executing the first one, when done returning to the FSBL that handoffs control to the second one and so on. But there is another way with the so called hooks: FsblHookBeforeBitstreamDload, FsblHoo
  9. I am trying to create an interrupt handler using Zynq. I am using the Zybo board and am using the Linux kernel from the following link: https://github.com/Xilinx/linux-xlnx.git. I have searched the Internet and I think I have everything set up properly but my handler never gets called in my driver. Here is my block design: ... and my interrupts set up in vivado: My dts file (attached here) contains the following: ps7_gpio_0: [email protected] { #gpio-cells = <2>; clocks = <&clkc 42>; compatible = "xlnx,zynq-gpio-1.0"; emio-gpio-width = <64>
  10. I am walking through the Getting Started With Zynq tutorial and am at a crossroads in the design. In step 5.2) of the tutorial: "After the design validation step we will proceed with creating a HDL System Wrapper. In the block design window, under the Design Sources tab, right-click on the block diagram file. We labeled it “design_1.bd” and select Create HDL Wrapper." Vivado gives me a pop up with two options and the tutorial doesn't provide any guidance. If I were not so new to FPGA design maybe the answer would be clear as day but as a beginner I wish these detail were more clear.
  11. I am attempting to sample values from the XADC and use those values to control a video display connected via VGA. Both of these parts work separately, but when I attempt to combine the hardware for the two, the XADC stops working. Specifically, the XADC still returns values, and those values still fluctuate slightly, but they don't represent the voltage anymore. I'm using the XADC in single channel mode, and have tried both channels 6 and 14. I've connected my analog input to PMOD-JA in the appropriate places for channel 6 and 14. Both of these channels function perfectly in my XADC o
  12. Hi every one, I'm trying to have My Smartphone (Sony Xperia Z2) MHL (TV-OUT) output in ZYBO HDMI input. When I use my laptop HDMI output (720p), the ZYBO works correctly, But when I connect My Smartphone via MHL(Mobile High-Definition Link) cable, Idon't have any output from VGA port. I must say that I tested phone MHL output on TV and it worked perfectly (1280*[email protected] & 1920*[email protected]). Please help me about this problem. Best regards. Sina shiri
  13. I'm trying to understand how to set up clocks and read data from a MIPI camera sensor. The sensor (Omnivision 5647) uses the MIPI CSI-2 protocol with D-PHY for the physical layer. The stage I am trying to get to is to be able to observer SoT (Start of Transmission) signals after which I can start parsing the CSI-2 protocol packets. In a small MIPI writeup located at http://archive.eetasia.com/www.eetasia.com/ART_8800715969_499489_TA_a466fca2_3.HTM there are 2 statements that are to be taken into consideration when trying to read data: "The high speed payload data from the transmitter i
  14. Hey there I'm thinking about purchasing a Zybo or Zedboard to Implement a SDR application. I'm in electronics engineering student with microcontroller history but brand new to FPGAs. I have a few questions about the vivado license, ISE vs Vivado for DSP applications. What exactly is it that the licence that Digilent sells offer that the webPack dosent? I have read here on the forums about some discrepancy between the Vado licenses and forgot it updates in this regard. Is the CihipScope offered in the wet pack now? I may later decide to purchase the SDR software package offered by AVN
  15. Hello, I am trying to program a new zedboard and am having trouble programming the ps portion of the board with a bare metal application. I am following the tutorial outlined in the zynq book, in which you load some pre-written c code, which should blink some leds. Unfortunately, I keep getting stuck on the programming of the board. I select run as -> Launch On Hardware and it gets about 89% of the way though the program and then hangs on "Launching: ps7_init". Has anyone seen this before? I have tried it on both Ubuntu 16.04 and Windows 10, and both give the same problem. Furthe
  16. Hello, I've recently purchased a PYNQ-Z1 dev board and am working to follow the examples in the Adam's MicroZed Chronicles. I'm able to successfully create the reference design in Vivado consisting of only ZYNQ PS, generate bitstream, Export HW Design and also create software projects that run on the target device in the SDK via JTAG. When attempting to create the boot image and flash, I've been unable to get the anywhere via QSPI or by placing the .bin file directly on the SD card and using the SD boot option switch. Here are the steps I've taken thus far:
  17. Hi everyone, I have seen discussion on this topic already in previous posts, but I am hoping someone has made a little progress and just hasn't posted yet. I'm hoping to be able to play audio (SFX & music) in a pong game I've made with Zybo. Does anyone have tips/experience on how to achieve this? FYI: I have an SD card, so that would be an option for audio file storage. Thanks for your time and effort! I am enjoying Zybo immensely so far. -Josh
  18. I'm new to FPGAs and the zynq. I'm interested in a zybo board and would like to know how to put an lvds output on the logic part of the zynq and how to get this connected to a framebuffer device I can use in linux to output graphics to?
  19. Hi I will my first zybo program Hello World like this link https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq/start?redirect=1id=zybo:gsg But I cant chose zybo option because it isnt My secreen view is here: why there is not zybo option ?
  20. I trying to use clock capable pin U15 on the Zynq using a Zybo board. According to ug865-Zynq-7000-Pkg-Pinout.pdf U15 is one of the pins that are clock capable (MRCC/SRCC): However I am getting the "Poor placement for routing..." error suggesting that I use "CLOCK_DEDICATED_ROUTE FALSE" which states is undesirable. Any idea what is going on here? I'm trying to use this with a high speed camera interface. thx
  21. Professors and researchers from University of Houston make use of Zedboard and Xilinx Vivado High Level Synthesisto implement the data encryption in the cloud computing. They explained this concept in two different conferences Field Programmable Logic (FPL) 2014 - Privacy Preserving Large Scale DNA Read-mapping in MapReduce Framework using FPGAs http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6927414 IEEE Cloud 2014 - PFC: Privacy Preserving FPGA Cloud - a Case Study of MapReduce http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=6973752&url=http%3A
  22. Hi every one. I was Created HLS Ip Core. This Core is a simple Image Filer, and the input for this Core is a matrix of picture that I built in Matlab, Now I'm trying to have a input from HDMI and filter output from VGA. In other words, I don't know "How create a simple block design in ZYBO for have HDMI input, VGA output and HLS IP CORE?" and "Which commands need to read frames from input in SDK sowftware?" Best regards. Abish SJ
  23. I have a quick question. I am trying to interface my Zybo board with a camera module (Arducam OV5640). The datasheet says that it uses 1.8/2.8V logic. In my XDC file do I simply use IOSTANDARD LVCMOS18 for each pin? I have tried this using the pmod connectors on the Zybo board and setting one pin high but when I check the voltage with a multimeter it reads 3.3V.
  24. Hello everyone; I am trying to boot Linux on Zybo using this tutorial: http://www.instructables.com/id/Embedded-Linux-Tutorial-Zybo/?ALLSTEPS I have load Boot,bin, devicetree.dtb uImage and uramdisk.image intor fat32 partition of my 16 Gb sd card. size of uramdisk.image is around 5 Mb. when I boot the Linux, I have the problem like this, BAD DATA CRC h Do you have any experience on that ? is the size of kernel correct?
  25. Abish sj

    BOOT IMAGE

    Hi guys, A screen shot as you see below is a SDK projects that has two system_wrapper_hw_platform folder. this program work properly when I program from JTAG, But when I'm trying to create BOOT Image, it's not work. How can I create the boot in this situation? please help me about this problem. thanks.