Search the Community

Showing results for tags 'zynq'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 106 results

  1. Hi every one, I'm trying to have My Smartphone (Sony Xperia Z2) MHL (TV-OUT) output in ZYBO HDMI input. When I use my laptop HDMI output (720p), the ZYBO works correctly, But when I connect My Smartphone via MHL(Mobile High-Definition Link) cable, Idon't have any output from VGA port. I must say that I tested phone MHL output on TV and it worked perfectly (1280*720@60Hz & 1920*1080@30Hz). Please help me about this problem. Best regards. Sina shiri
  2. I'm trying to understand how to set up clocks and read data from a MIPI camera sensor. The sensor (Omnivision 5647) uses the MIPI CSI-2 protocol with D-PHY for the physical layer. The stage I am trying to get to is to be able to observer SoT (Start of Transmission) signals after which I can start parsing the CSI-2 protocol packets. In a small MIPI writeup located at http://archive.eetasia.com/www.eetasia.com/ART_8800715969_499489_TA_a466fca2_3.HTM there are 2 statements that are to be taken into consideration when trying to read data: "The high speed payload data from the transmitter is transmitted on both the edges of the High speed differential clock (DDR clock)" "The high speed differential clock and the data transmitted from the transmitter are 90 degrees out of phase and with the data being transmitted first." Using VHDL and Vivado, how do I create logic to successfully read data from this sensor? I have the following code written (with notes/questions) but I'm pretty sure its wrong. It was put together based on my limited understanding and reading various other source code that perform similarly: http://pastebin.com/FGvChHis I was told that in order to derive the correct delay value I would have to sample the output clock at the rising edge. If it is not 1, decrement the delay value. If it is 1, increment the delay value. This way the delay should always be within +/- 1 of the ideal value. I have experimented with this code and tried to see how many SoT's I can detect but its very low (<10 per minute). This is probably due to random chance. Really need help on this one!
  3. Hey there I'm thinking about purchasing a Zybo or Zedboard to Implement a SDR application. I'm in electronics engineering student with microcontroller history but brand new to FPGAs. I have a few questions about the vivado license, ISE vs Vivado for DSP applications. What exactly is it that the licence that Digilent sells offer that the webPack dosent? I have read here on the forums about some discrepancy between the Vado licenses and forgot it updates in this regard. Is the CihipScope offered in the wet pack now? I may later decide to purchase the SDR software package offered by AVNET, or at least individually accumulate those licenses as my budget allows. So how dose the webpack version limit my ability to integrate with the software elements(currently unable to find the said software package) used for SDR & DSP development? What are the limitations of the Pmod interface if I were to go with the Zybo and later try to coonect to a FMC interposer/Analog Devices ACD boards? Im reading the zybo book but any links to more learning resources would be greatly appreciated. I'm ready to pull the trigger on a purchase today as soon as I get these questions answered. Looked high and low for a phone number
  4. Hello, I am trying to program a new zedboard and am having trouble programming the ps portion of the board with a bare metal application. I am following the tutorial outlined in the zynq book, in which you load some pre-written c code, which should blink some leds. Unfortunately, I keep getting stuck on the programming of the board. I select run as -> Launch On Hardware and it gets about 89% of the way though the program and then hangs on "Launching: ps7_init". Has anyone seen this before? I have tried it on both Ubuntu 16.04 and Windows 10, and both give the same problem. Furthermore, I am able to run "connect arm hw" in XMD console and it appears to work fine. I am also able to program just the PL fine as well through Vivado or SDK. I also don't think it is my header pin settings? I have them all set to gnd, which should be boot from JTAG. Other Info: Operating System: Tried on both Windows 10 and Ubuntu 16.04 (Virtual Machine) Vivado/SDK Version: Tried on both 2016.2 and 2016.4 ZedBoard: Latest Rev (D?) Power Source: Provided wall plug into US 120v 60hz
  5. Hello, I've recently purchased a PYNQ-Z1 dev board and am working to follow the examples in the Adam's MicroZed Chronicles. I'm able to successfully create the reference design in Vivado consisting of only ZYNQ PS, generate bitstream, Export HW Design and also create software projects that run on the target device in the SDK via JTAG. When attempting to create the boot image and flash, I've been unable to get the anywhere via QSPI or by placing the .bin file directly on the SD card and using the SD boot option switch. Here are the steps I've taken thus far: Create new Vivado Design project referencing the Digilent Arty-Z7-20 Board Added the ZYNQ PS Connected M_AXI_GP0_ACLK to FCLK_CLK0 and fast foward....generated Bitstream Exported HW Design Create Sample Hello World Project in SDK (tested successfully and runs perfectly via JTAG) Generate FSBL Create Boot Image - Added elf bootloader from FSBL - Added bitstream from HW Export -- This generates the bin file used to program flash in the next step Program Flash - Selected the HW Platform Exported from Vivado - Used Image file created above - No Offset - Flash Type qspi_single Flash programming completes successfully. I select QSPI, power cycle the board and fail to get the done LED on the board indicating that the FPGA bitstream has been downloaded. I place the same bitfile named boot.bin on the SD card and get the same result. Nothing. Any suggestions? Is there some strange delta w/ the Digilent board I'm using that I don't know about. Additionally, the example bin file provided by Digilent works perfectly.
  6. Hi everyone, I have seen discussion on this topic already in previous posts, but I am hoping someone has made a little progress and just hasn't posted yet. I'm hoping to be able to play audio (SFX & music) in a pong game I've made with Zybo. Does anyone have tips/experience on how to achieve this? FYI: I have an SD card, so that would be an option for audio file storage. Thanks for your time and effort! I am enjoying Zybo immensely so far. -Josh
  7. I'm new to FPGAs and the zynq. I'm interested in a zybo board and would like to know how to put an lvds output on the logic part of the zynq and how to get this connected to a framebuffer device I can use in linux to output graphics to?
  8. Hi I will my first zybo program Hello World like this link https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq/start?redirect=1id=zybo:gsg But I cant chose zybo option because it isnt My secreen view is here: why there is not zybo option ?
  9. I trying to use clock capable pin U15 on the Zynq using a Zybo board. According to ug865-Zynq-7000-Pkg-Pinout.pdf U15 is one of the pins that are clock capable (MRCC/SRCC): However I am getting the "Poor placement for routing..." error suggesting that I use "CLOCK_DEDICATED_ROUTE FALSE" which states is undesirable. Any idea what is going on here? I'm trying to use this with a high speed camera interface. thx
  10. Professors and researchers from University of Houston make use of Zedboard and Xilinx Vivado High Level Synthesisto implement the data encryption in the cloud computing. They explained this concept in two different conferences Field Programmable Logic (FPL) 2014 - Privacy Preserving Large Scale DNA Read-mapping in MapReduce Framework using FPGAs http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6927414 IEEE Cloud 2014 - PFC: Privacy Preserving FPGA Cloud - a Case Study of MapReduce http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=6973752&url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel7%2F6968679%2F6973706%2F06973752.pdf%3Farnumber%3D6973752 The project is also sponsored by NATO. http://www.uh.edu/news-events/stories/2016/March/032316ShiNATO
  11. Hi every one. I was Created HLS Ip Core. This Core is a simple Image Filer, and the input for this Core is a matrix of picture that I built in Matlab, Now I'm trying to have a input from HDMI and filter output from VGA. In other words, I don't know "How create a simple block design in ZYBO for have HDMI input, VGA output and HLS IP CORE?" and "Which commands need to read frames from input in SDK sowftware?" Best regards. Abish SJ
  12. malkauns

    Zybo board 1.8V logic

    I have a quick question. I am trying to interface my Zybo board with a camera module (Arducam OV5640). The datasheet says that it uses 1.8/2.8V logic. In my XDC file do I simply use IOSTANDARD LVCMOS18 for each pin? I have tried this using the pmod connectors on the Zybo board and setting one pin high but when I check the voltage with a multimeter it reads 3.3V.
  13. Hello everyone; I am trying to boot Linux on Zybo using this tutorial: http://www.instructables.com/id/Embedded-Linux-Tutorial-Zybo/?ALLSTEPS I have load Boot,bin, devicetree.dtb uImage and uramdisk.image intor fat32 partition of my 16 Gb sd card. size of uramdisk.image is around 5 Mb. when I boot the Linux, I have the problem like this, BAD DATA CRC h Do you have any experience on that ? is the size of kernel correct?
  14. Abish sj

    BOOT IMAGE

    Hi guys, A screen shot as you see below is a SDK projects that has two system_wrapper_hw_platform folder. this program work properly when I program from JTAG, But when I'm trying to create BOOT Image, it's not work. How can I create the boot in this situation? please help me about this problem. thanks.
  15. Hardent release board support package file and design file of Petalinux for ZYBO. Check out their blog: http://www.hardent.com/electronic-FPGA-design-consulting-services/petalinux-zybo-bsp-now-available-to-download/
  16. Hello, How can I communicate with the SD card in bare metal application at Zybo board< There are some free FAT32/16 filesystem stacks, but how to make them work with Zybo HW? Is there any reference solution for file read/write?
  17. Takeways: 1. Maximize the usage of the Xilinx Zynq 7000 resources 2. Understand the nuances and internal workings of the Xilinx Zynq 7000 3. Trade-off performance vs. energy consumption Complexity of systems implemented using FPGA's are exponentially growing in a rapid pace. As a result of it most of the common design issues that a designer come across with ASIC SoC are becoming relevant with FPGA as well. If we consider Xilinx Zynq 7000 Programmable SoC, there is considerable processing power on the compute side. A simple migration is insufficient to achieve the same performance as discrete chips and also achieving performance and implementation benefits of such a complex FPGA would be very less. Estimating or identification of system performance and crucial bottlenecks much before writing RTL not just reduces the development time but also increases the Quality of Results. During this event we will be talking about how performance analysis and architecture exploration of a Zynq 7000 based System in the early stage of system development ensures that the right FPGA platform is selected and achieves optimal partitioning of the application onto the fabric. To Register, Click here
  18. Mehdim

    how to define constraint

    Hello guys; Can anyone help me how to assign a port to specific pin in Vivado? I am using custom port on AX_GPIO module and I want to add it to one of PMOD connectors; I am using this command to connect it to V12 set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { gpio2_io_o }]; it works fine, but if I want to assign a vector port to some pins(for example gpio2_io_o[7:0] ) what should I do to define constraint?
  19. Dear Community. I've recently bought a Zybo Zynq board and i'm having some getting started problems. Im known with both C and VHDL programming before but i've never had such a multi-purpose FGPA, dualcore board before. I tried following some basic tutorials, like: https://reference.digilentinc.com/zybo:gsg http://www.zynqbook.com/ and several youtube led blinks. But I'm experiencing different problems with all of them. My board isnt listed in the Vivado 2015 > new project > boards list I can't find the right settings to get the leds to the GPIO Or when I find a "pre made tutorial led blink" its made on a earlier version of vivado and i can only open it read only, or it edits the files causing errors. I did however get the Xililinux running at the moment ( but thats just copying bootfiles to a sd card) Is there anyone who has a tutorial which is compatible with Vivado2015 and can get me started trying to do some actual programming in this new and unknown environment to me. Any help would be greatly appreciated. And sorry to ask such a question Greetings
  20. i need a simple project in that zynq ps read dada from a ip counter can you help me?
  21. Hello guys, I followed this tutorial "Embedded linux on zybo" http://www.instructables.com/id/Embedded-Linux-Tutorial-Zybo/ and everything works like a charm, I compiled the linux kernel and u-boot from digilent github, as a next step I said i'll be debugging Linux C apps. I'm trying hard to debug a linux application coded in xilinx SDK (2015.1) according to the follwoing two links: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/SDK_Doc/tasks/sdk_t_linux_application_debugging_system_debugger.htm what happens that when i try to press Debug, i got in the debug perspective .. "Target does not support Processes service" Am i supposed to use different Linux kernel (i.e. Petalinux) or Am is supposed to use different uramdisk ? Please let me know what am i missing???
  22. Jnadin

    Jtag HS3

    Hi All, I am having issues using the JTAG HS3 with my PCB that uses zynq 7020 chip. I have tried using it with zc702 and zedboard and these seems to work however plugging the device into my board the device is not found. I am guess there is something I have missed when designing the board. I have the lines pulled high to 3V3 which then go to the FPGA. Is there any thing else I need to consider for the PCB to work with this device? was anyone able to design a board that had this JTAG working? Kind Regards, J. Nadin
  23. Hello, The older Atlys boards had a Spartan-6 FPGA which meant the highest progressive resolution supported by the HDMI input and output was 720p (which was always frustrating). I was wondering if that had changed with the newer Series 7 devices like the Zybo or Nexys Video boards? I noticed that hamster was able to get 1080i working. Are SERDES even able to do 1080p theoretically? Thanks for your help! Tim 'mithro' Ansell
  24. I've een going through the Zybo Embedded Hands on Tutorial and I ------ - Cannot find zynq_ZYBO_config file for compiling UBOOT. It's not there in the master and master-next branch.... - Cannot find ramdisk Image on ZYBO webpage... - Cannot proceed further... IMHO the "tutorial" is not organized properly at all... Is anyone at Digilent maintaining / reviewing all these documents before putting them up on the internet ? Can anyone provide these files if they have ? Thank You....
  25. Hi All, I am newbie to zynq board, eagerly started to learn. I have digilent HDMI FMC card it supports 8,10,12 bits color depth. I am trying with pixel width 10-bits with xilinx zynq zc702 board. previously we used Avnet HDMI FMC card it supports only 8-bit pixel width.Now we are in need to move with 10 and 12-bits pixel width. 1. What are the things needed to use digilent fmc card with zync zc702 board. 2.Where i can get drivers (c-code libs) for digilent fmc card. 3.While its operating in 10-bit mode should i connect it with 10-bit color depth output of laptop? 4.Can i use Avnet fmc card drivers for this digilent fmc card too ? (in this case i need to change EDID content w.r.t digilent fmc card) 5. Kindly help me regarding this, It would be a great help to me..!!! I Tried as Mentioned Below : 1.I am not having the digilent fmc card drivers to use and compile it with my application C-code so i used with some changes of Avnet fmc card driver C-codes. Also chnaged the EDID content w.r.t digilent fmc card ref Document. 2.I used lenova G580 lap to connect HDMI o/p from laptop to FMC card using HDMI cable.digilent fmc card mode is pixel width is 10-bit but while looking at Graphics card properties of Lap shows that the color depth is 32-bit output, I am sure whther it will support the 10-bit mode digilent fmc card. 3.Any how, While running it I am facing the error message which is given below, Error: ADV7611 has NOT locked on incoming video, aborting ! Thanks, Ramesh