Search the Community

Showing results for tags 'zynq'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 107 results

  1. Greetings all, I'm facing some issues in running my PikeOS project on zc702 board Following are some brief steps that i took to make PikeOS's project i selected a pikeOS integrated project, using devel-apex demo template Board Parameters Description: Xilinx Zynq-7000 All Programmable SoC ZC702 Evaluation kit. Architecture: arm Processor: v7hf Boot Strategy: uboot_dtb then in project Configuration, set path of binery to run on partition. on boot, it generate a file name, apex-devel-zynq-zc702-uboot in order to boot this project on board using sd card few more files are required. This is where i'm lost, can't figure how to generate those files, or where to find then. Hopefully Someone can help me. Thank You.
  2. Hello, I recently purchased a Zybo Zynq 7000 development board and would like to implement some modulating guitar effects like chorus, phasing, and flanging with the FPGA and was wondering if anyone has had any experience in this area.
  3. Hi people, What I mean is that, can I write a program such that it can program the FPGA while executing? Thanks!
  4. Hi, I am trying to rebuild the arty z7 petalinux BSP as per the instructions given by them here https://github.com/Digilent/petalinux-bsps/wiki/Quick-Start-Guide-for-Arty-Z7. But when I try the command $ petalinux-boot --jtag --prebuilt 3, I get an error saying [skaat27@localhost Digilent-Arty-Z7-Linux-BD-v2016.2]$ petalinux-boot --jtag --prebuilt 3 ERROR: No subsystem configuration file can be find in the project. sh: lsb_release: command not found webtalk failed:Invalid tool in the statistics file:petalinux-yocto! webtalk failed:Failed to get PetaLinux usage statistics! Anybody knows what the issue is? Karthik
  5. Hi, Is there a good example to establish communication between Zynq and Microblaze processor on Zybo? I am looking to understand how to get both these processors to talk to each other, share data etc. I'm aware of this Xilinx app note: https://www.xilinx.com/support/documentation/application_notes/xapp1093-amp-bare-metal-microblaze.pdf But i'm looking for something simpler and on Zybo. Thanks.
  6. Dear digilent, I am interested to retarget the following design to a zybo or spartan 6 FPGA. The design link is: https://reference.digilentinc.com/reference/pmod/pmodsf/start ( Nexys 3 VHDL Example - ISE 13.4 ). Could you please advise me how to do it? Thank you. F
  7. Dear all, I hated the fact the Zybo Zynq does not have a proper D/A converter on its own. So I programmed a VHDL 1-bit delta sigma modulator according to this Link. The delta sigma modulator is working as a charm, but I want to be able to set the frequency of the waveforms i am generating. I want to set the frequency of the waveform by using an 1-10V input signal. I am okay with C and VHDL but I have never used the block designs or Zynq IP & GPIO Blocks.. The PMOD connector connected to the fpga is already in use so I guess my options are. Use a external microcontroller with ADC and use SPI to the PS part of the zybo zynq. Use the XADC connect it to the PS and of course use a voltage divider or something Microcontroller and just bit bang the values directly to the PL side Are there any suggestions on the easiest way of doing this ? ps: Is it possible to do something similar to interrupts in VHDL
  8. Hi, I am new at this area. My current project required to know the use of HDMI and VGA port of Zybo board. As a starting point I got a sample demo project(https://github.com/Digilent/Zybo-hdmi-in) by digilent but that was done in Vivado 2016.4. I am working on Vivado 2017.2 windows PC. I successfully convert that project in current version and able to generate Bit stream successfully. The problem is when I lunch SDK, it gives me errors. Can anyone help me? Or can anyone gives me some simple project which from where I can get idea about how to use HDMI and VGA port? Thanks.
  9. hello, i'm new born baby in embedded system. I want to establish a communication between ADC Board to Zedboard(PL-section-xc7z020) via LPC-FMC connector. please tell me lpc fmc pin out and how those pins connected to PL(FPGA) Section of zynq (like any diagram). please help me, Thank you.
  10. Hello I'm using Digilent JTAG-HS3 Programming Cable with a Zynq 7000 based board. With HS3, I'm able to program the PL of the Zynq using Vivado 2016.4. In my application, I need to have an extension cable connection the Zynq to the HS3; this extension cable is about 1m long. In case I set the reference voltage on the base board to 2.5V, I'm able to connect to the Zynq, program it and flash the QSPI memory. On the other hand, if I change the reference voltage on the base board to 3.3V, I'm not able to detect the Zynq at all. In Vivado, I obtain the error message: ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210299A1F0C9. Are there any specific requirements to make the extension cable work with HS3 and Zynq using 3.3 reference voltage?
  11. Hello everyone. I'm using a Zedboard and I'm running Xillinux on it. I'm getting info from the XADC using Xillybus but the values I'm getting don't seem to make sense. I'm converting VP/VN, Vaux0P/Vaux0N and Vaux8P/Vaux8N. They're in bipolar mode. I'm just seeing what the values are without feeding them any voltage, just the noise. I'm getting values like 8200, 8A00, 7F00 and so. According to the XADC doc, only the 12 MSB contain actual information about the conversion, being the other 4 bits just for accuracy. So that'd make them 820, 8A0, 7F0... Translating that into voltages, it would be as if I was feeding it 500mV (when it's under 800h) or -500 mV (when it's over 800h). Reasonable values would start at least with a 0, like 073 for example. At first I thought I was getting these values because I wasn't feeding it with any actual voltage source, hence the random behaviour. But then I tried following this tutorial on how to set up the XADC just using block design (without using any embedded linux) and I got the values through serial port. I modified the helloworld.c from that tutorial so I could print the hex values of the conversion (the raw data was an u32 so I just typed %xl in the printf) and values where like 0740, 0d56, and so. Removing the last 4 bits, that'd make it 074, 0d5 which I think are very reasonable values for noise. So, should I be worried about the values I'm getting from Xillybus? Is that an expected behaviour because of the noise? Is something wrong with the way I'm using/instantiating my XADC? UPDATE: I have tried feeding the XADC and values from Xillybus keep the same while in that demo app (the tutorial I mentioned) I'm getting them correctly so I assume this something wrong with the XADC but I can't seem to know what. Might it be the offset?? Thanks in advance!
  12. dzabakh

    UART interrupt example

    Hello everyone! I am facing a problem while working with a project on Zybo. I have UART1 input (the input connected with microUSB port) enabled in my project and I want to make a simple user interface in a standalone application. I have already found several examples of such applications but the thing is that I don't want the program to continuously examine the input - I want the processor to get an interrupt every time the user makes an input. Is there any example of how this has to be done? Thank you in advance.
  13. mihai5

    Timer on bare metal app

    Hi, I want to measure elapsed time in a bare-metal application on the Xilinx Zynq SoC(zedboard). I included "xtime_l.h" and used XTime_GetTime(&tStart) and XTime_GetTime(&tEnd) to populate tStart and tEnd. The difference tEnd – tStart always gives me 0 for whatever instructions I put between XTime_GetTime(&tStart) and XTime_GetTime(&tEnd). Instructions between XTime_GetTime(&tStart) and XTime_GetTime(&tEnd) that I put are: ————————————- XTime_GetTime(&tStart); print(“Hello World\n\r”); for(int i=0;i< 1000 ;i++) { sum += i; } Xil_Out32(0x43c00000, 0x5); Xil_Out32(0x7aa00000, 0x5555); NumberOfPattern = Xil_In32(0x43c00004); XTime_GetTime(&tEnd) ————————————- I need to mention that i did not configure the PL part to include an axi_timer IP. I did not do this because, as i read, this uses the global timer in the zynq Soc whose counter increases every two clock cycles. Can someone to show me where is the mistake and give me some advices?
  14. dbkincaid

    Arty-Z7 GPIO0 access

    Hello, I am having trouble with the last bit of my project where I have modified the video_demo of the Arty_Z7 example I added a 32bit GPIO to the Zynq7 in Vivado and exported it to the SDK. Note I am 'not' using the AXI, I am using the direct GPIO access. The .bit is automated from the block design. I have read and re-read the example in SDK for initiating a port read for this XGPIOPS Here is the code I think has an issue: (at define block and globals) #define GPIO_DEVICE_ID XPAR_XGPIOPS_0_DEVICE_ID XGpioPs Gpio; /* The driver instance for GPIO Device. */ (at beginning of function) XGpioPs_Config *ConfigPtr; u32 InputData; (later where the code is executed) /* Initialize the GPIO driver. */ ConfigPtr = XGpioPs_LookupConfig(GPIO_DEVICE_ID); status = XGpioPs_CfgInitialize(&Gpio,ConfigPtr,ConfigPtr->BaseAddr); /* Set the direction for all 32 pins to be input. */ XGpioPs_SetDirection(&Gpio, 0,0); /* Read the state of the data so that it can be verified, press any key to stop */ while (!XUartPs_IsReceiveData(UART_BASEADDR)) { InputData = XGpioPs_Read(&Gpio, 0); xil_printf("%08x\n\r",InputData); }; What this is supposed to do is blast the UART with the GPIO_0 data coming from the fabric, I confirmed on the Vivado side using ILA that the GPIO_0 data is running counters, etc as I designed it. What I actually get from the .ELF run is a constant value. I think this means I am either reading from the wrong place or I am somehow misunderstanding the function and just repeating the 32bit address of the memory location (instead of the data) Can anyone look this over and point out my error?
  15. Hello to al, The system is built on the Zybo board in standalone mode. So far I had success sending interrupts from PL via GPIO. In order to reduce complexity I decided to try sending interrupts directly as it is shown on the included diagram. The RTL module is a simple counter sending a pulse once in a period of time. ILA confirmed the pulse. The application is supposed to count 50 interrupt events and quit. However, no triggering is happening. Clock freq is 50 MHz and a counter is 16 bit. The C-code is taken from two sources: Xilinx Timer-interrupt example and Avnet interrupt tutorial controlling brightness with PWM. The issue in my opinion is that I can't find the parameter called INTERRUPT_ID. The file xparameter.h has nothing related to IRQ interrupt or anything else related to the INTERRUPT_ID or INTC_ID. Below is the last used C-code snapshot. #include <stdio.h> #include "platform.h" #include "xparameters.h" #include "xscugic.h" #include "xil_printf.h" #include "xil_exception.h" #define INTC_INTERRUPT_ID 84 // IRQ [0] #define INTC XScuGic #define INTC_HANDLER XScuGic_InterruptHandler #define INTC_DEVICE_ID XPAR_PS7_SCUGIC_0_DEVICE_ID // =0 static INTC Intc; unsigned int LED = 0; // Interrupt counter void PIsr(void *InstancePtr){ // INTERRUPT SERVICE ROUTINE(ISR) LED ++; } int SetupInterruptSystem() { int result; XScuGic *IntcInstancePtr = &Intc; XScuGic_Config *IntcConfig; IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); if (IntcConfig == NULL) { return XST_FAILURE; } result = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig, IntcConfig->CpuBaseAddress); if (result != XST_SUCCESS) { return XST_FAILURE; } /* Connect the interrupt handler */ result = XScuGic_Connect(IntcInstancePtr, INTC_INTERRUPT_ID, (Xil_ExceptionHandler) PIsr, 0); if (result != XST_SUCCESS) { return result; } /* Enable the interrupt for the controller device. */ XScuGic_Enable(IntcInstancePtr, INTC_INTERRUPT_ID); Xil_ExceptionInit(); Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)INTC_HANDLER, IntcInstancePtr); Xil_ExceptionEnable(); /* Enable non-critical exceptions */ return XST_SUCCESS; } int main(void) { int status = XST_SUCCESS; xil_printf("\nLED=%d\n",LED); status = SetupInterruptSystem(); if (status != XST_SUCCESS) { return XST_FAILURE; } while (LED < 50) { } xil_printf("LED=%d",LED); return 0; } Hope someone could share insights and educate me. Thank you very much!
  16. Hello to everyone, I want to show the temperature data with Teraterm . I get from PMOD TMP3 . But I have to design the PMOD TMP3 IP and I do not know what is the difference with led_ip_design on the link there. https://forums.xilinx.com/xlnx/attachments/xlnx/gendis/16930/1/adding ip.pdf Can you help me? How can I show the temperature data?
  17. ihab.adly

    Zybo board

    I recently bought a board Zybo Zynq-7000 manufactured by your company and contains the Xilinx XC7Z010-1CLG400C chip. However, when I tried to get the free version of the Vivado to operate my board, I received the following message: "Failed Export Compliance Verification". I am now stuck with my board and cannot make any use of it. I am living in Egypt and there was no restriction whatsoever getting the board, so how come I am not able to get the necessary software to use it. Please advise.
  18. I just received my Arty Z7! I'm trying to get a basic example up and running. Since there aren't any tutorials up yet on the Arty Z7 start page: https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start so I tried to follow the "Getting Started with Zynq" example for the Zedboard: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zedboard-getting-started-with-zynq/start I created the project using the Arty Z7 20 Vivado board files. Everything went smoothly until I try run the code example (Launch on Hardware). I get: ERROR : Memory write error at 0x100000. APB AP transaction error, DAP status f0000021 and the example fails to run. From discussions of this error on the Xilinx forums, it sounds the DDR is possibly misconfigured. I also tried to run the example out of OCM (ps7_ram_0/1), but got the same error with the address corresponding to OCM base address, so maybe the DDR isn't the problem. Any ideas what I might be doing wrong? Happy to provide more information if that would help. Thanks!
  19. Question to experts: What is the fastest way for saving continuous data coming from PL on Zynq without requiring the processor you would recommend? The data rate is expected to vary in the range 4-8 MB/s. Preferred processor operational mode is standalone. Options considered so far are BRAM, OCM and DDR3. All of these options seems require custom HDL coding to interface Zynq memory. Before comitting to such effort I'd like to hear opinions from the community. Thank you!
  20. Hi, I wanted to know if there are any official plans to support the Python Productivity for Zynq - PYNQ packages for Arty Arty Z7-10 or Arty Z7-20. Since there are very likely going to be overlaps in their target audiences, hobbyists and new learners. It would be awesome for Arty Z7-x to be an officially supported platform.
  21. I recently purchased the Zybo, zynq development board, along with a MIC3 so that I could hopefully take in audio from the PMOD port and then process it in Arm processor, and finally output it through the audio output port. I'm having trouble getting the audio routed with the IP in vivado. I'm fairly new to the vivado IP integrator but I have some experience creating verilog projects. Has anyone used the MIC3 with the zybo, or know how to get the audio from a MIC3 in one of the PMOD ports, into the ARM for proccessing? Any help would be greatly appreciated.
  22. Hi guys, I bought a zybo board and did a simple hello world project to test the functionality, but it didn't work. Here's what I've done: After exporting hardware and creating sdk projects, I downloaded the bitstream & program into zybo as usual. But the board wouldn't run the program normally(It doesn't terminate and doesn't print helloworld). So I debug the board using xsdb, step by step, and find out that disassembly result is not the same as elf file displayed in SDK. xsd shows that data at 0x100000 is 0xea020049; however, in the sdk, the data should be 0xea000049, as shown in the second picture. If I keep on stpi, since it'll go to the wrong place, CPU will finally goto infinite loop. xsdb% connect tcfchan#0 xsdb% targets 1 APU 2 ARM Cortex-A9 MPCore #0 (Running) 3 ARM Cortex-A9 MPCore #1 (Running) 4 xc7z010 xsdb% fpga -f "design_1_wrapper_hw_platform_0/design_1_wrapper.bit" 100% 1MB 1.8MB/s 00:01 xsdb% targets 2 xsdb% source "design_1_wrapper_hw_platform_0/ps7_init.tcl" xsdb% rst; ps7_init; ps7_post_config; Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0xffffff28 (Suspended) Info: ARM Cortex-A9 MPCore #1 (target 3) Stopped at 0xffffff34 (Suspended) xsdb% dow "hello_world/Debug/hello_world.elf" Downloading Program -- C:/Xilinx/Zybo/project_2/project_2.sdk/hello_world/Debug/hello_world.elf section, .text: 0x00100000 - 0x001016eb section, .init: 0x001016ec - 0x00101703 section, .fini: 0x00101704 - 0x0010171b section, .rodata: 0x0010171c - 0x00101733 section, .data: 0x00101738 - 0x00101bab section, .eh_frame: 0x00101bac - 0x00101baf section, .mmu_tbl: 0x00104000 - 0x00107fff section, .init_array: 0x00108000 - 0x00108003 section, .fini_array: 0x00108004 - 0x00108007 section, .bss: 0x00108008 - 0x0010802f section, .heap: 0x00108030 - 0x0010a02f section, .stack: 0x0010a030 - 0x0010d82f 100% 0MB 0.4MB/s 00:00 Setting PC to Program Start Address 0x00100000 Successfully downloaded C:/Xilinx/Zybo/project_2/project_2.sdk/hello_world/Debug/hello_world.elf xsdb% mrd 0x100000 16 100000: EA020049 100004: EA040025 100008: EA00002B 10000C: EA00003B 100010: EA000032 100014: E320F000 100018: EA000000 10001C: EA00000F 100020: F92DD91F 100024: ED3F1FBB 100028: ED6D0B20 10002C: EEF11A10 100030: 00001004 100034: 00001A10 100038: FFFF1004 10003C: EFF1019E elf file contents: Disassembly of section .text: 00100000 <_vector_table>: 100000: ea000049 b 10012c <_boot> 100004: ea000025 b 1000a0 <Undefined> 100008: ea00002b b 1000bc <SVCHandler> 10000c: ea00003b b 100100 <PrefetchAbortHandler> 100010: ea000032 b 1000e0 <DataAbortHandler> 100014: e320f000 nop {0} 100018: ea000000 b 100020 <IRQHandler> 10001c: ea00000f b 100060 <FIQHandler> 00100020 <IRQHandler>: 100020: e92d500f push {r0, r1, r2, r3, ip, lr} 100024: ed2d0b10 vpush {d0-d7} 100028: ed6d0b20 vpush {d16-d31} 10002c: eef11a10 vmrs r1, fpscr 100030: e52d1004 push {r1} ; (str r1, [sp, #-4]!) 100034: eef81a10 vmrs r1, fpexc 100038: e52d1004 push {r1} ; (str r1, [sp, #-4]!) 10003c: eb00019e bl 1006bc <IRQInterrupt> So, the problem is, WHY is the DRAM data partially wrong??? I almost doubt DRAM works normally, but I just bought the board a week ago lol.
  23. Recently I had to make a standalone Zynq project that had multiple .ELF files all residing on an SD card. The board had to somehow know, while being powered off, which .ELF file to boot from. So how to do this? The answer is in the FSBL file. Currently, in Vivado's 2014.2 SDK, the FSBL can handle multiple "partitions" (that's how any Second Stage BootLoader is called, in our case the .ELF files) by executing the first one, when done returning to the FSBL that handoffs control to the second one and so on. But there is another way with the so called hooks: FsblHookBeforeBitstreamDload, FsblHookAfterBitstreamDload, FsblHookBeforeHandoff. With these handy functions you can halt the FSBL and do whatever (for example read the switches) before the bitstream file has been downloaded, after or right before the SSBL is being booted. Here's a simple usage example: let's you have three .ELF files on the SD card and you want to select which one to boot with the on-board switches. First of all you generate an FSBL project, then open the image_mover.c file from the src folder. Scroll down to line 440 and change the code as bellow: if (PLPartitionFlag) { if (PartitionAttr & ATTRIBUTE_PS_IMAGE_MASK) { Status = FsblHookBeforeBitstreamDload(); if (Status != XST_SUCCESS) { fsbl_printf(DEBUG_GENERAL,"FSBL_BEFORE_BSTREAM_HOOK_FAILrn"); OutputStatus(FSBL_BEFORE_BSTREAM_HOOK_FAIL); FsblFallback(); } else { HeaderPtr = &PartitionHeader[ExecutionAddress]; PartitionDataLength = HeaderPtr->DataWordLen; PartitionImageLength = HeaderPtr->ImageWordLen; PartitionExecAddr = HeaderPtr->ExecAddr; PartitionAttr = HeaderPtr->PartitionAttr; PartitionLoadAddr = HeaderPtr->LoadAddr; PartitionChecksumOffset = HeaderPtr->CheckSumOffset; PartitionStartAddr = HeaderPtr->PartitionStart; PartitionTotalSize = HeaderPtr->PartitionWordLen; ExecAddress = PartitionExecAddr; } } } Open the fsbl_hooks.c file and add the following global variable: extern u32 ExecutionAddress; Go to the FsblHookBeforeBitstreamDload function and change it: u32 FsblHookBeforeBitstreamDload(void) { u32 Status; u32 dwSws; Status = XST_SUCCESS; // The first partition would usually be the PL bitstream, so we're // skipping it. do { dwSws= Xil_In32(SWS_BASEADDRESS) & 0x03; } while(dwSws == 0x00); ExecutionAddress = dwSws; xil_printf("Selected partition %drn", swSws); /* * User logic to be added here. Errors to be stored in the status variable * and returned */ fsbl_printf(DEBUG_INFO,"In FsblHookBeforeBitstreamDload function rn"); return (Status); } ExecutionAddress will hold the value of the first two switches and point to the corresponding partition. And finally here's how the "Create Zynq Boot Image" SDK utility would look like when creating the BOOT.BIN that'll go onto the SD: That's it! Hope it helps someone (or even myself sometime in the future when I forget all this ).
  24. I am trying to create an interrupt handler using Zynq. I am using the Zybo board and am using the Linux kernel from the following link: https://github.com/Xilinx/linux-xlnx.git. I have searched the Internet and I think I have everything set up properly but my handler never gets called in my driver. Here is my block design: ... and my interrupts set up in vivado: My dts file (attached here) contains the following: ps7_gpio_0: ps7-gpio@e000a000 { #gpio-cells = <2>; clocks = <&clkc 42>; compatible = "xlnx,zynq-gpio-1.0"; emio-gpio-width = <64>; gpio-controller ; gpio-mask-high = <0xc0000>; gpio-mask-low = <0xfe81>; interrupt-parent = <&ps7_scugic_0>; interrupts = <0 59 4>; reg = <0xe000a000 0x1000>; } ; I am trying to hook interrupt 91 on the PS that is triggered from PL using AXI GPIO. I have subtracted 32 from 91 hence the <0 59 4> in the dts file. My interrupt_v1_0 IP simply creates a 10ns pulse every second. I expect to see my interrupt function being called in the driver every second once I load my bitstream and driver but this does not happen. Can someone please check and tell me what I am doing wrong? I have attached my driver, dts and code for my interrupt IP here. Thanks. zynq-zybo.dts interrupt.vhd driver.c
  25. I am walking through the Getting Started With Zynq tutorial and am at a crossroads in the design. In step 5.2) of the tutorial: "After the design validation step we will proceed with creating a HDL System Wrapper. In the block design window, under the Design Sources tab, right-click on the block diagram file. We labeled it “design_1.bd” and select Create HDL Wrapper." Vivado gives me a pop up with two options and the tutorial doesn't provide any guidance. If I were not so new to FPGA design maybe the answer would be clear as day but as a beginner I wish these detail were more clear. Copy generated wrapper to allow user edits Let VIvado manage wrapper and auto-update The window also states;"You can either add or copy the HDL wrapper file to the project. Use copy option if you would like to modify this file." The next step moves on to generate a bitstream file so I'm going to assume that this file will not be edited any longer. I wish the tutorial would provide a bit more context to the steps laid out and how the operations used in this simple project would/could be used in another project. So far I appears that once I'm done this this tutorial I will only have learned how to accomplish the same task, only with a bit more confidence. After step 6 I am given another window the tutorial does not make any mention of. The window is titled Launch Runs with text; "Launch the selected synthesis or implementation runs." and provides 3 choices. Launch runs on local host: Generate scrips only Number of jobs [2] {with option to change value} There is also a choice of Launch directory. On this one I'm totally clueless. I realize that Diligent is not responsible for changes in the Vivado IDE but I as a company focused on education I think it could do better on updating tutorials to accurately reflect the changes in Vivado. I would also LOVE to see more Zybo tutorials, they are far and few between on the net. The book is alright but a bit difficult to navigate to topics the relevant for beginners. If anyone could respond with instruction on how I SHOULD have proceed with these options and what any of these options really mean I would appreciate it, as I have now come across some warnings in the TCL console about needing a "AXI BFM license to run".