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Found 113 results

  1. deppenkaiser

    Arty-Z7-20 board

    Hello, i have since a few days a new arty-z-20 board and i like to learn from the rare examples for that board. I found one example which seems to be the base for Linux (Arty-Z7-20-linux_bd-master). This example was made with the Vivado 2016.4 Suite, but i use the current Vivado Suite (2017.3). In that example are two ip`s that could not be upgraded, because they no longer exists in the current Vivado Suite. Where can i get some working examples with Vivado 2017.3 and higher Support for my new Arty-Z7-20 board? My first Arty board was the Artix-7 "original" board. I had found all the examples that i needed to learn from the beginning to the full scale microblaze architecture. I made good experiences, but now i'am not happy with that arty-Z7-20 board! How do i build the simplest Zynq architecture with UART and "bare metal" OS? How do i build the very easiest Linux architecture and what ip's do i need for that? I have a lot more questions... Thank you...
  2. Hi there, I'm connecting Pmod NAV: 9-axis IMU Plus Barometer with Trenz board (Trenz TE0701-06 + TE0720). I have been following tutorial to add PMOD in the Vivado design. I using Vivado 2016.2 version. But, in the board section, there is no available board component as it is shown in tutorials which is for evaluation boards, like the one below: In my case, there is no board component: Could you help me in how to make connections with Zynq board, I'm currently using? Did anyone came across this? Thanks a lot!
  3. Colin

    Zybo tutorial help

    i currently have a project where i need to produce a tone from a zybo board and to familiarise myself with the board i downloaded the pdf from and the zip files but and i do the tutorials step for step but when i try to run the programme on the board nothing happens im using vivado 2017.1 i have the ports set to 115200 baud when i import the c code i get a warning from xparamaters.h i asked my project manager and they said its because im not using costraints but the turtorial specifically mentions not using constraints can anyone tell me what am i doing wrong despite the fact im doing the tutorial step for step?
  4. Greetings, I am currently working on a Digilent Zybo Trainer Board with a Zynq 7010 chip. Everything works fine from hardware up to software running on the board as long as it is launched directly from the Xilinx SDK. However, the software hangs up indefinitely whenever the Xil_In32() function is called ONLY when booting from non-volatile memory (QSPI flash or SD card). I have followed the prescribed process of making an FSBL, creating a boot image (with (bootloader)FSBL.elf, hw_wrapper.bit, main_project.elf) and programming the BOOT.bin file to flash memory successfully. The FSBL calls the 'ps7_init()' and ps7_post_config()' functions. My research shows that this issue revolves around enabling the level shifters, but as far as I can tell this occurs in the ps7_post_config() function. Any help would be appreciated. Details: Hardware: Zybo Trainer Board (Zynq 7010) Hardware peripherals: XADC Wizard, AXI GPIO Project: standalone C project Vivado 2017.2 Xilinx SDK 2017.2 OS: Windows 7 Enterprise SP1
  5. Hi there I am selling my Zinq-Z1 board ( zynq 7020 ) She is "as new". I put Arty Z7 in the title because these two board are so similar (not the same colour of pcb, and the Pynq has one thing more: a mic) mine is a pynq. My price is 99€ plus shipment , you can find easily on ebay my announce, there are some photos, I also sell on ebay my Spartan 6 board (papilio duo and computing shield) Thx & Regards B.
  6. Hello, I am trying to generate a Digital Output by using the Zynq Processing System. I tought using the Pmod would be easy to handle but I am already failing to design the hardware to activate the Pmod MIO. Do you know a (or similar) tutorial for that? Can you give some advises how to realize it? Thank You! Best regards
  7. Greetings all, I'm facing some issues in running my PikeOS project on zc702 board Following are some brief steps that i took to make PikeOS's project i selected a pikeOS integrated project, using devel-apex demo template Board Parameters Description: Xilinx Zynq-7000 All Programmable SoC ZC702 Evaluation kit. Architecture: arm Processor: v7hf Boot Strategy: uboot_dtb then in project Configuration, set path of binery to run on partition. on boot, it generate a file name, apex-devel-zynq-zc702-uboot in order to boot this project on board using sd card few more files are required. This is where i'm lost, can't figure how to generate those files, or where to find then. Hopefully Someone can help me. Thank You.
  8. Hello, I recently purchased a Zybo Zynq 7000 development board and would like to implement some modulating guitar effects like chorus, phasing, and flanging with the FPGA and was wondering if anyone has had any experience in this area.
  9. Hi people, What I mean is that, can I write a program such that it can program the FPGA while executing? Thanks!
  10. Hi, I am trying to rebuild the arty z7 petalinux BSP as per the instructions given by them here But when I try the command $ petalinux-boot --jtag --prebuilt 3, I get an error saying [[email protected] Digilent-Arty-Z7-Linux-BD-v2016.2]$ petalinux-boot --jtag --prebuilt 3 ERROR: No subsystem configuration file can be find in the project. sh: lsb_release: command not found webtalk failed:Invalid tool in the statistics file:petalinux-yocto! webtalk failed:Failed to get PetaLinux usage statistics! Anybody knows what the issue is? Karthik
  11. Hi, Is there a good example to establish communication between Zynq and Microblaze processor on Zybo? I am looking to understand how to get both these processors to talk to each other, share data etc. I'm aware of this Xilinx app note: But i'm looking for something simpler and on Zybo. Thanks.
  12. Dear digilent, I am interested to retarget the following design to a zybo or spartan 6 FPGA. The design link is: ( Nexys 3 VHDL Example - ISE 13.4 ). Could you please advise me how to do it? Thank you. F
  13. Dear all, I hated the fact the Zybo Zynq does not have a proper D/A converter on its own. So I programmed a VHDL 1-bit delta sigma modulator according to this Link. The delta sigma modulator is working as a charm, but I want to be able to set the frequency of the waveforms i am generating. I want to set the frequency of the waveform by using an 1-10V input signal. I am okay with C and VHDL but I have never used the block designs or Zynq IP & GPIO Blocks.. The PMOD connector connected to the fpga is already in use so I guess my options are. Use a external microcontroller with ADC and use SPI to the PS part of the zybo zynq. Use the XADC connect it to the PS and of course use a voltage divider or something Microcontroller and just bit bang the values directly to the PL side Are there any suggestions on the easiest way of doing this ? ps: Is it possible to do something similar to interrupts in VHDL
  14. Hi, I am new at this area. My current project required to know the use of HDMI and VGA port of Zybo board. As a starting point I got a sample demo project( by digilent but that was done in Vivado 2016.4. I am working on Vivado 2017.2 windows PC. I successfully convert that project in current version and able to generate Bit stream successfully. The problem is when I lunch SDK, it gives me errors. Can anyone help me? Or can anyone gives me some simple project which from where I can get idea about how to use HDMI and VGA port? Thanks.
  15. hello, i'm new born baby in embedded system. I want to establish a communication between ADC Board to Zedboard(PL-section-xc7z020) via LPC-FMC connector. please tell me lpc fmc pin out and how those pins connected to PL(FPGA) Section of zynq (like any diagram). please help me, Thank you.
  16. Hello I'm using Digilent JTAG-HS3 Programming Cable with a Zynq 7000 based board. With HS3, I'm able to program the PL of the Zynq using Vivado 2016.4. In my application, I need to have an extension cable connection the Zynq to the HS3; this extension cable is about 1m long. In case I set the reference voltage on the base board to 2.5V, I'm able to connect to the Zynq, program it and flash the QSPI memory. On the other hand, if I change the reference voltage on the base board to 3.3V, I'm not able to detect the Zynq at all. In Vivado, I obtain the error message: ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210299A1F0C9. Are there any specific requirements to make the extension cable work with HS3 and Zynq using 3.3 reference voltage?
  17. Hello everyone. I'm using a Zedboard and I'm running Xillinux on it. I'm getting info from the XADC using Xillybus but the values I'm getting don't seem to make sense. I'm converting VP/VN, Vaux0P/Vaux0N and Vaux8P/Vaux8N. They're in bipolar mode. I'm just seeing what the values are without feeding them any voltage, just the noise. I'm getting values like 8200, 8A00, 7F00 and so. According to the XADC doc, only the 12 MSB contain actual information about the conversion, being the other 4 bits just for accuracy. So that'd make them 820, 8A0, 7F0... Translating that into voltages, it would be as if I was feeding it 500mV (when it's under 800h) or -500 mV (when it's over 800h). Reasonable values would start at least with a 0, like 073 for example. At first I thought I was getting these values because I wasn't feeding it with any actual voltage source, hence the random behaviour. But then I tried following this tutorial on how to set up the XADC just using block design (without using any embedded linux) and I got the values through serial port. I modified the helloworld.c from that tutorial so I could print the hex values of the conversion (the raw data was an u32 so I just typed %xl in the printf) and values where like 0740, 0d56, and so. Removing the last 4 bits, that'd make it 074, 0d5 which I think are very reasonable values for noise. So, should I be worried about the values I'm getting from Xillybus? Is that an expected behaviour because of the noise? Is something wrong with the way I'm using/instantiating my XADC? UPDATE: I have tried feeding the XADC and values from Xillybus keep the same while in that demo app (the tutorial I mentioned) I'm getting them correctly so I assume this something wrong with the XADC but I can't seem to know what. Might it be the offset?? Thanks in advance!
  18. dzabakh

    UART interrupt example

    Hello everyone! I am facing a problem while working with a project on Zybo. I have UART1 input (the input connected with microUSB port) enabled in my project and I want to make a simple user interface in a standalone application. I have already found several examples of such applications but the thing is that I don't want the program to continuously examine the input - I want the processor to get an interrupt every time the user makes an input. Is there any example of how this has to be done? Thank you in advance.
  19. mihai5

    Timer on bare metal app

    Hi, I want to measure elapsed time in a bare-metal application on the Xilinx Zynq SoC(zedboard). I included "xtime_l.h" and used XTime_GetTime(&tStart) and XTime_GetTime(&tEnd) to populate tStart and tEnd. The difference tEnd – tStart always gives me 0 for whatever instructions I put between XTime_GetTime(&tStart) and XTime_GetTime(&tEnd). Instructions between XTime_GetTime(&tStart) and XTime_GetTime(&tEnd) that I put are: ————————————- XTime_GetTime(&tStart); print(“Hello World\n\r”); for(int i=0;i< 1000 ;i++) { sum += i; } Xil_Out32(0x43c00000, 0x5); Xil_Out32(0x7aa00000, 0x5555); NumberOfPattern = Xil_In32(0x43c00004); XTime_GetTime(&tEnd) ————————————- I need to mention that i did not configure the PL part to include an axi_timer IP. I did not do this because, as i read, this uses the global timer in the zynq Soc whose counter increases every two clock cycles. Can someone to show me where is the mistake and give me some advices?
  20. dbkincaid

    Arty-Z7 GPIO0 access

    Hello, I am having trouble with the last bit of my project where I have modified the video_demo of the Arty_Z7 example I added a 32bit GPIO to the Zynq7 in Vivado and exported it to the SDK. Note I am 'not' using the AXI, I am using the direct GPIO access. The .bit is automated from the block design. I have read and re-read the example in SDK for initiating a port read for this XGPIOPS Here is the code I think has an issue: (at define block and globals) #define GPIO_DEVICE_ID XPAR_XGPIOPS_0_DEVICE_ID XGpioPs Gpio; /* The driver instance for GPIO Device. */ (at beginning of function) XGpioPs_Config *ConfigPtr; u32 InputData; (later where the code is executed) /* Initialize the GPIO driver. */ ConfigPtr = XGpioPs_LookupConfig(GPIO_DEVICE_ID); status = XGpioPs_CfgInitialize(&Gpio,ConfigPtr,ConfigPtr->BaseAddr); /* Set the direction for all 32 pins to be input. */ XGpioPs_SetDirection(&Gpio, 0,0); /* Read the state of the data so that it can be verified, press any key to stop */ while (!XUartPs_IsReceiveData(UART_BASEADDR)) { InputData = XGpioPs_Read(&Gpio, 0); xil_printf("%08x\n\r",InputData); }; What this is supposed to do is blast the UART with the GPIO_0 data coming from the fabric, I confirmed on the Vivado side using ILA that the GPIO_0 data is running counters, etc as I designed it. What I actually get from the .ELF run is a constant value. I think this means I am either reading from the wrong place or I am somehow misunderstanding the function and just repeating the 32bit address of the memory location (instead of the data) Can anyone look this over and point out my error?
  21. Hello to al, The system is built on the Zybo board in standalone mode. So far I had success sending interrupts from PL via GPIO. In order to reduce complexity I decided to try sending interrupts directly as it is shown on the included diagram. The RTL module is a simple counter sending a pulse once in a period of time. ILA confirmed the pulse. The application is supposed to count 50 interrupt events and quit. However, no triggering is happening. Clock freq is 50 MHz and a counter is 16 bit. The C-code is taken from two sources: Xilinx Timer-interrupt example and Avnet interrupt tutorial controlling brightness with PWM. The issue in my opinion is that I can't find the parameter called INTERRUPT_ID. The file xparameter.h has nothing related to IRQ interrupt or anything else related to the INTERRUPT_ID or INTC_ID. Below is the last used C-code snapshot. #include <stdio.h> #include "platform.h" #include "xparameters.h" #include "xscugic.h" #include "xil_printf.h" #include "xil_exception.h" #define INTC_INTERRUPT_ID 84 // IRQ [0] #define INTC XScuGic #define INTC_HANDLER XScuGic_InterruptHandler #define INTC_DEVICE_ID XPAR_PS7_SCUGIC_0_DEVICE_ID // =0 static INTC Intc; unsigned int LED = 0; // Interrupt counter void PIsr(void *InstancePtr){ // INTERRUPT SERVICE ROUTINE(ISR) LED ++; } int SetupInterruptSystem() { int result; XScuGic *IntcInstancePtr = &Intc; XScuGic_Config *IntcConfig; IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); if (IntcConfig == NULL) { return XST_FAILURE; } result = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig, IntcConfig->CpuBaseAddress); if (result != XST_SUCCESS) { return XST_FAILURE; } /* Connect the interrupt handler */ result = XScuGic_Connect(IntcInstancePtr, INTC_INTERRUPT_ID, (Xil_ExceptionHandler) PIsr, 0); if (result != XST_SUCCESS) { return result; } /* Enable the interrupt for the controller device. */ XScuGic_Enable(IntcInstancePtr, INTC_INTERRUPT_ID); Xil_ExceptionInit(); Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)INTC_HANDLER, IntcInstancePtr); Xil_ExceptionEnable(); /* Enable non-critical exceptions */ return XST_SUCCESS; } int main(void) { int status = XST_SUCCESS; xil_printf("\nLED=%d\n",LED); status = SetupInterruptSystem(); if (status != XST_SUCCESS) { return XST_FAILURE; } while (LED < 50) { } xil_printf("LED=%d",LED); return 0; } Hope someone could share insights and educate me. Thank you very much!
  22. Hello to everyone, I want to show the temperature data with Teraterm . I get from PMOD TMP3 . But I have to design the PMOD TMP3 IP and I do not know what is the difference with led_ip_design on the link there. ip.pdf Can you help me? How can I show the temperature data?
  23. ihab.adly

    Zybo board

    I recently bought a board Zybo Zynq-7000 manufactured by your company and contains the Xilinx XC7Z010-1CLG400C chip. However, when I tried to get the free version of the Vivado to operate my board, I received the following message: "Failed Export Compliance Verification". I am now stuck with my board and cannot make any use of it. I am living in Egypt and there was no restriction whatsoever getting the board, so how come I am not able to get the necessary software to use it. Please advise.
  24. I just received my Arty Z7! I'm trying to get a basic example up and running. Since there aren't any tutorials up yet on the Arty Z7 start page: so I tried to follow the "Getting Started with Zynq" example for the Zedboard: I created the project using the Arty Z7 20 Vivado board files. Everything went smoothly until I try run the code example (Launch on Hardware). I get: ERROR : Memory write error at 0x100000. APB AP transaction error, DAP status f0000021 and the example fails to run. From discussions of this error on the Xilinx forums, it sounds the DDR is possibly misconfigured. I also tried to run the example out of OCM (ps7_ram_0/1), but got the same error with the address corresponding to OCM base address, so maybe the DDR isn't the problem. Any ideas what I might be doing wrong? Happy to provide more information if that would help. Thanks!
  25. Question to experts: What is the fastest way for saving continuous data coming from PL on Zynq without requiring the processor you would recommend? The data rate is expected to vary in the range 4-8 MB/s. Preferred processor operational mode is standalone. Options considered so far are BRAM, OCM and DDR3. All of these options seems require custom HDL coding to interface Zynq memory. Before comitting to such effort I'd like to hear opinions from the community. Thank you!