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Found 398 results

  1. I am trying to make RAM work on my zybo; however, it keeps failing the memory test, I have tried additionally, I have tried setting up different "memory part" in the settings in vivado according to these reference manuals Do you know what I might be doing wrong?
  2. Hey, I have a very novice question and really just need a high level answer, but I'll get straight to the point! I'm using the Zybo z7-10 with Vivado and Vitis 2019.2. This is what I would like to do, and I'm trying to do it in VHDL: Write some data from software to control registers that I define Perform some processing on this data Use DMA to write some results to DDR I would like the firmware piece that does the processing to be a block in the BD. I've gone through many forums, and it seems at one time the preferred way was to package an IP. I found out about adding an RTL module, which seemed more appropriate because I want to be able to modify quickly as I go, and in the same project. Based on what I've read, I was thinking to make an RTL module with a Slave AXI-lite interface (not sure how to do the registers though?), then use a master AXI-stream to pump the results to a Xilinx DMA IP block. I've been passing Synthesis but getting different Implementation errors ("failed to stitch checkpoint", "*.vhd is a black box") doing trial and error with this. All I've done in terms of the code is try to define the entity port to have those two interfaces, either copying from other IPs or using the Language Template (for AXI stream). Is there a good example in VHDL of a barebones AXI peripheral like this, that will pass Implementation? Once that works, I can get into adding those registers and the processing logic. Thank you!
  3. Hi all, You know how when you first power on the board, the LEDs cycle in a pattern and the HDMI TX displays a rainbow test pattern? I was wondering if the sources/a Vivado project for that behavior exists somewhere, it would be cool to see how all that is done. Thanks!
  4. Totally new to all this. 73 year old grandpa, retired engineer, returning to grad school, microelectronics concentration. Lots of technology catch-up to do. So, starting with VHDL. I must self-teach VHDL and need my first FPGA. Can someone help me understand these 3 possible choices for someone in my position: (1) Basys MX3 PIC32MX, (2) Nexys A7-100T, (3) Zybo Z7. Don't want to buy anything too complex, but I have to get the basics with ability to grow. Many questions about compatibility, accessories, programming... Can you help me get started?
  5. Hello, I bought the Zybo-Z7-20 eval board. I downloaded the DMA project from repository and it ran fine in the EDK. So, far so good. However, when I started to re-run synthesis, there were error in the synthesis as to could not synthesize the Zynq part. Below is the error message from the synth log. I would appreciate anyone noticing this error showing how to get past it. Seems like I am missing some setup files or folder, not sure what .... ============================ Near the end of Error Log: ============================ couldn't open "i:/Rafi/Dropbox/Engr_consulting/Digilent_Xilinx/Zybo_eval_Xilinx_Zynq/Example_Prjs/Zybo-Z7-20-DMA-2018.2-1/vivado_proj/Zybo-Z7-20-DMA.runs/system_processing_system7_0_0_synth_1/.Xil/Vivado-7036-Rafi-GamePC//incrSyn/system_processing_system7_0_0.genomesNotDumped": no such file or directory Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 1045.969 ; gain = 379.242 INFO: [Common 17-83] Releasing license: Synthesis 19 Infos, 101 Warnings, 0 Critical Warnings and 1 Errors encountered. synth_design failed ERROR: [Common 17-69] Command failed: Vivado Synthesis failed INFO: [Common 17-206] Exiting Vivado at Mon Apr 13 07:07:59 2020... ============================ Vivado version: 2018.2
  6. Hope you all are fine, I downloaded Digilent/Zybo-Z7-20-HDMI from I have upgraded the ip's, it was displaying output on monitor. Then I have created the ip of sobel edge detection and added the ip in block diagram. After solving some clocking issues, bitstream has been generated. After launching to sdk, when I Launch on Hardware (System Debugger), output doesn't display. Below is block diagram, please guide me
  7. vinivj

    DSRC transceiver for FPGA

    Is there any DSRC transceiver module (IEEE 802.11p), the wireless communication protocol for vehicles, that is compatible with FPGA board? I would like to interface it with Zybo board. Could someone provide input on this?
  8. Does the demo design ( support 1920x720 HDMI path-throught? The Product guide for dvi2rgb and rgb2dvi IP mentions that "Resolutions supported: 1920x1080/60Hz down to 800x600/60Hz (148.5 MHz – 40 MHz)" but I am not sure if the specific resolution 1920x720 is supported. Thank you
  9. Hi, apparently it is easy to damage something by playing around with the XADC-port (of a Zybo-Z7 in this case). I want to read the charging curve of a capacitor. How I thought this could be done I simulated in LTSpice: 300mv are much less than the maximum 1V and I added R5 and R3 because there are no preresisitors inside XADC-ports. I guess this way my hardware should survive the first time converting an analog voltage curve into digital value. But I'm, just guessing so the two questions I have about this are 1. Is this safe? 2. Is there a better way to do this? and also 3. How sensible are the XADC-Ports really? How high do currents and/or voltages have to be to cause damages? Are maybe the only important rules to prevent short circuits through XADC-hardware by placing a preresistor and prevent voltages above 3.3V? Thank you! /edit Question #4 Would a combination of resistors (one would be enough I think) and Zener-diodes (breakdown at 1V), as you can see below, securely protect any hardware onboard of any mistakes done outside XADC-Pmod? This is just a result of my tiny little knowledge of analog elecronics. Simulation does agree but that is just simulation. Maybe in reality and for a very short time there still could be constellations causing voltages and/or currents that could damage my board... Or is this schematic below really a secure protection? Depending on how XADC-hardware looks inside, theoretically a short circuit current would cause high voltages which should also be taken by the diodes, ...I guess. So are resistors maybe not even needed and only Zener-diodes would already give a safe protection of hardware damages?
  10. hey there I am a beginner to zynq. I have bought a zybo board. I am using vivado version 2015.4. I followed the below link to add zybo board file to vivado: then I this tutorial: but it did not work. in this tutorial says: but when I select Hello world demo, I see the below attached image. it says that could you please tell me what I should do? thanks in advance.
  11. Hello All, I am having an issue with running the Master Polled example on I2C with the zynq. I have a base design that is set up and runs the self test and repeated start examples and completes them. My issue is that I hooked up an I2C sensor, added pullup resistors, and it is failing. The only thing I have changed in SDK is that I have found the address of my I2C sensor, 0x57, and put it in place of 0x55. I can place my block design and what not here for referencing. Update - I have assigned I2C pins to W19 and W20 to SCL and SDA respectively.
  12. rcjhy8

    Zybo External LED Control

    Hi all, New to the FPGA world as I was tasked a project to help familiarize myself with the programming and function of how FPGAs work. As you can all infer, I am in need of some help on a specific project that I am doing. I am using a ZYBO Zynq 7000 development board, and Vivado 2019.1. What I am trying to do is control an external sensor, or LED through some user interface. I have seen a lot of tutorials that use the on-board LEDs, and if you press a button, it displays that value in binary in a command terminal. My task that I was to do is be able to turn on and off an external LED connected to the ZYBO through the command terminal. It seems I can connect a simple circuit with a LED and a resistor to the PMOD pins that are power and ground. What the command terminal would let me do is then essentially cut power to that pin, therefore turning the LED off. Please let me know if this is probable, and/or how I should task to complete it. Thanks, Russell
  13. SDK fatal error:xgpio.h no such file or directory I am using: Vivado 2016.4 Design Tools Windows10 on a Lenovo Ideapad Zybo dev. board with the Zynq7020 While following the first exercise in The Zynq Book Tutorial. I encountered several errors but they seemed harmless enough since I was able to successfully create and export a bitstream. But now I am wondering if those warning and errors from the IP Integrator stage is causing my inability to build the project LED_test_tut_C.c code in the SDK, receiving fatal error:xgpio.h:No such file or directory. When looking in "C:\Zynq_Book\first_zynq_design\first_zynq_design.sdk\LED_test_bsp\ps7_cortexa9_0\include", there is indeed no "xgpio.h" file. Could this be due to errors I received in the during implementation? Such as: WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'first_zynq_system_i/axi_gpio_0/gpio_io_o[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [C:/Zynq_Book/first_zynq_design/first_zynq_design.runs/impl_1/.Xil/Vivado22392YogaFlex/dcp_3/first_zynq_system_axi_gpio_0_0.edf:3791] I think the first of which was: "ERROR: [Ipptcl 7-1] Could not find packager TCL script '/scripts/ip/ipx.tcl'" Another was: ERROR: [IP_Flow 19-2234] Failed to initialize IP Tcl interpreter '::ipgui_xilinx_com_ip_processing_system7_5_5': couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory while executing"source C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl" invoked from within "interp eval ::ipgui_xilinx_com_ip_processing_system7_5_5 ]" and CRITICAL WARNING: [IP_Flow 19-973] Failed to create IP instance 'first_zynq_system_processing_system7_0_0'. Error during customization. The list continues (can provide full more tcl messages and logs) but I was able to generate a bitstream. Another aggravating factor could be that I ran into the 2012 Microsoft C/C++ Redistributable compatibility issue when starting the SDK from within the IDE. To solve that problem I renamed xvcdredlist.ext in the "C:\Xilinx\SDK\2016.4\tps\win64" folder and launched from the Start menu. Since most of the errors encountered have to do with input/output and GPIO, I kind of think and hope that the root problem has to do with the following warning thrown in the Vivado 2016.4 IDE / IP Integrator synthesis/ implementation: "WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'first_zynq_system_i/axi_gpio_0/gpio_io_o[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. " My question is whether all these errors received in the implementation stage are related to the error in the SDK. If that is the case than would solving the following error ( the very first error) solve all? if so how would I go about that? If in your answer you could as much explanation as needed to help me understand how to troubleshoot this myself, it would be most appreciated. As I am new to FPGA development. This is the tcl command that started it all: "create_bd_cell -type ip -vlnv c_addsub_0" and produced this: couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory ERROR: [IP_Flow 19-2234] Failed to initialize IP Tcl interpreter '::ipgui_design_1_c_addsub_0_0': couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory while executing "source C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl" invoked from within "interp eval ::ipgui_design_1_c_addsub_0_0 ]" If these warnings and errors are unrelated could I successfully download the bitstream to my Zybo board without fixing the errors encountered while using the IP Integrator and only fixing the fatal error: xgpio.h: No such file or directory in the SDK? If so, is the best way to do that? Finally just to recap my questions are to help me understand the warning/error messages and ultimately resolve the xgpio.h no such file error, and as follows in no particular order: What dose first_zynq_systemj/axi_gpio[0] is not directly connected to top level port mean? As this would help me solve the IOSTANDARD error. Would renaming xvcredlist.exe create problems elsewhere? What is this tcl command trying to achieve and why is giving the error? create_bd_cell -type ip -vlnv c_addsub_0 Why can I see xgpio.h in the project explorer tab under src/LED_test_tut1C.c but not under the C/C++ projects tab? How can I fix the xgpio.h: no such file or Directory in the SDK? Thank you for your attention. I apologize for the wordy post and welcome anyone who can shed light on any of these questions.
  14. Hello, I’m having problems with sending large amount of data from ZYBO to a computer. For example, when I tried to send image data (640x480) at the maximum baud rate, the computer didn’t receive all data. But when baud rate was set to 256000, all data were received. It seems like UART buffer is overflowing. How to solve this problem? Best regards, Toni
  15. Kampi

    XADC - AD7 sampled on AD14

    Hello, I have a Zybo Board (Version 1 Rev. and I have a strange Issue with my XADC which samples the input for the channel AD7 on the channel AD14. Please take a look at my setup. I want to use the differential Channelpair 7 and 15 (like in the Photo - upper row VIn and lower row ground from my voltage source). My software gives me the results for channel 14 and 15 and the value for channel 7 stays constant even when I increase or decrease the input voltage. Only channel 14 and 15 change her values. I expect that channel 14 stays constant and channel 7 change his value. Temperature: 46.1576 Degree Celsius Vcc INT: 0.9961 V Vref+: 1.25 V Vref-: 3.00 V Channel 7: 2351 Channel 14: 26032 Channel 15: 32767 My code looks like this #include "stdio.h" #include "xparameters.h" #include "xadcps.h" XAdcPs XAdc; XAdcPs_Config* ConfigPtr; int main() { ConfigPtr = XAdcPs_LookupConfig(XPAR_XADC_DEVICE_ID); if(ConfigPtr == NULL) { xil_printf("Invalid XADC configuration!"); return XST_FAILURE; } XAdcPs_CfgInitialize(&XAdc, ConfigPtr, ConfigPtr->BaseAddress); if(XAdcPs_SelfTest(&XAdc) != XST_SUCCESS) { xil_printf("Self test failed!"); return XST_FAILURE; } XAdcPs_Reset(&XAdc); XAdcPs_SetSeqChEnables(&XAdc, XADCPS_SEQ_CH_AUX07 | XADCPS_SEQ_CH_AUX14 | XADCPS_SEQ_CH_AUX15); XAdcPs_SetSequencerMode(&XAdc, XADCPS_SEQ_MODE_CONTINPASS); xil_printf("Start...\n\r"); while(1) { u32 Temp = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_TEMP); printf("Temperature: %.4f Degree Celsius\n\r", XAdcPs_RawToTemperature(Temp)); u32 VCCInt = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_VCCINT); printf("Vcc INT: %.4f V\n\r", XAdcPs_RawToVoltage(VCCInt)); u32 VREFp = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_VREFP); printf("Vref+: %.2f V\n\r", XAdcPs_RawToVoltage(VREFp)); u32 VREFn = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_VREFN); printf("Vref-: %.2f V\n\r", XAdcPs_RawToVoltage(VREFn)); u32 Ch7 = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_AUX_MIN + 7); xil_printf("Channel 7: %lu\n\r", Ch7); u32 Ch14 = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_AUX_MAX - 1); xil_printf("Channel 14: %lu\n\r", Ch14); u32 Ch15 = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_AUX_MAX); xil_printf("Channel 15: %lu\n\r", Ch15); xil_printf("-------------\n\r"); for(u32 i = 0x00; i < 0xFFFFFF; i++); } return XST_SUCCESS; } With the following XDC file: ##Pmod Header JA (XADC) set_property IOSTANDARD LVCMOS33 [get_ports Vaux14_v_n] set_property IOSTANDARD LVCMOS33 [get_ports Vaux14_v_p] set_property PACKAGE_PIN N16 [get_ports Vaux14_v_n] set_property IOSTANDARD LVCMOS33 [get_ports Vaux6_v_n] set_property IOSTANDARD LVCMOS33 [get_ports Vaux6_v_p] set_property IOSTANDARD LVCMOS33 [get_ports Vaux7_v_n] set_property IOSTANDARD LVCMOS33 [get_ports Vaux7_v_p] set_property IOSTANDARD LVCMOS33 [get_ports Vaux15_v_n] set_property IOSTANDARD LVCMOS33 [get_ports Vaux15_v_p] So what is going wrong here?
  16. I'm trying to run the Zybo Z7 Pcam 5C Demo... i'm really new at this, the instructions say: ********************************************************** To generate the project: 1. Open Vivado 2017.4 2. In the tcl console, type "cd [this directory]/proj" and press enter. 3. Type "source ./create_project.tcl" and press enter to generate the block design for the project. To run the demo from SD card: 1. Copy bin/BOOT.bin to the root of your SD card. 2. Set the boot jumper on the Zybo Z7 to SD. 3. Insert the SD card into the Zybo Z7 and power it on. ************************************************** I'm using Vivado 2017.4 and i've copied the board_files to vivado software. After the point 3. (Type "source ./create_project.tcl") I get 7 warnings about some pins... am im doing something wrong here? I'm a newbie. Can you help me out to make the demos work, thanks in advance! ********************************************************************************************************* ## create_root_design "" WARNING: [BD 41-1306] The connection to interface pin /sw_gpio/gpio_io_i is being overridden by the user. This pin will not be connected as a part of interface connection GPIO WARNING: [BD 41-1731] Type mismatch between connected pins: /rgb2dvi_0/aRst_n(rst) and /v_axi4s_vid_out_0/locked(undef) WARNING: [BD 41-1306] The connection to interface pin /blur_edge_detect_0/ap_start is being overridden by the user. This pin will not be connected as a part of interface connection ap_ctrl WARNING: [BD 41-1306] The connection to interface pin /color_to_bw_0/ap_start is being overridden by the user. This pin will not be connected as a part of interface connection ap_ctrl WARNING: [BD 41-1306] The connection to interface pin /invert_0/ap_start is being overridden by the user. This pin will not be connected as a part of interface connection ap_ctrl Wrote : <C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/> Wrote : <C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/ui/bd_c954508f.ui> WARNING: [BD 41-721] Attempt to set value '50000000' on disabled parameter 'C_S_AXI_LITE_FREQ_HZ' of cell '/MIPI_D_PHY_RX_0' is ignored WARNING: [BD 41-721] Attempt to set value '200000000' on disabled parameter 'kRefClkFreqHz' of cell '/MIPI_D_PHY_RX_0' is ignored WARNING: [BD 41-721] Attempt to set value '100000000' on disabled parameter 'kRefClkFreqHz' of cell '/video_dynclk' is ignored INFO: [] /video_dynclkFREQ_HZ of 100000000 propagated into CONFIG.kRefClkFreqHz INFO: [] /MIPI_CSI_2_RX_0Verified that video_aclk frequency can handle RxByteClkHS frequency. AXI-Stream bandwidth 600000000 Pix/s >= PPI bandwidth 134400000.0 Pix/s INFO: [] /MIPI_D_PHY_RX_0FREQ_HZ of 50000000 propagated into CONFIG.C_S_AXI_LITE_FREQ_HZ INFO: [] /MIPI_D_PHY_RX_0FREQ_HZ of 200000000 propagated into CONFIG.kRefClkFreqHz INFO: [] /MIPI_D_PHY_RX_0FREQ_HZ of 84000000 propagated onto RxByteClkHS Wrote : <C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/> VHDL Output written to : C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/synth/system.vhd VHDL Output written to : C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/sim/system.vhd VHDL Output written to : C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/hdl/system_wrapper.vhd make_wrapper: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1317.461 ; gain = 79.957 # set sdk_dir $origin_dir/sdk # set hw_list [glob -nocomplain $sdk_dir/*hw_platform*] # if {[llength $hw_list] != 0} { # foreach hw_plat $hw_list { # file delete -force $hw_plat # } # } # set sdk_list [glob -nocomplain $sdk_dir/*] # set sdk_list [lsearch -inline -all -not -exact $sdk_list "../sdk/.keep"] # if {[llength $sdk_list] != 0} { # exec xsct -eval "setws -switch ../sdk; importproject ../sdk" # } update_compile_order -fileset sources_1
  17. birca123

    ZYBO Image Processing

    Hello, is there any image processing library that can be used for standalone applications on ZYBO? Thanks, Toni
  18. Hi, I am working on a project where i use four UART for an application, all four uart lines sends and receives approx. 20 bytes of characters and expects 20 bytes o character in every 16 milliseconds. And the data transfer will be continuous. NOTE : All four UARTs, are on PL side and controlled by PS of my zynq SoC.. NODE B : Zybo NODE A : Subsystem The UART communication is between NODE A and NODE B. NODE A sends data to NODE B, in turn NODE B should receive the data and reply with an acknowledgement. In this case NODE B is my Zybo Node A is another subsystem. So the data transmission is initiated by NODE A and the control is with NODE A. NODE A will Enable the data transmission for all four UARTs. Now the problem which i am facing is, when NODE A enables the transmission for any two of the UART lines the data transmission is smooth, the problem arises only when i enable the other two. Which means the zybo is not capable of attending to those interrupts which is simultaneously coming from NODE A through four UART lines. My data contains Start byte and Stop byte, Both Start and stop byte are same character. I will attach a my Interrupt handler for reference. **************NOTE************** UART IP on PL side : UART16550 Type of UART : Interrupt driven. Software used : Vivado 2018.3 and SDK Bare metal software. UART interrupt priority : equal priority for all four UARTs. ********************************** I am not very sure about how to use four UARTs efficiently with my Zybo . Please help me with the problem, any inputs from your side will be appreciated. The following is my UART interrupt handler. *************************************************************************** static void RW1RecvHandler(void *CallBackRef, unsigned int EventData) { int i, ch, RecvCount, index; RecvCount = EventData; // repeat this loop for all chars received, i.e., for all ReceivedCount i = 0; while (i < RecvCount) { ch = RW1_RecieveBuffer[i++]; // get the received char from the buffer if(RW1_Start_byte_flag == 1) { // Stop Byte Check for RW1 if (ch == 0xc0) { // Ignore one of the two successive start byte characters if (RW1_ReceivedCount > 1) { RW1_Start_byte_flag = 0; RW1_Buffer[RW1_ReceivedCount++] = ch; RW1_Frame_complete_flag = 1; } } else { if ((index = RW1_ReceivedCount) < TEST_BUFFER_SIZE) { RW1_Buffer[index] = ch; RW1_ReceivedCount++; } else RW1_Start_byte_flag = 0; } } // Start Byte Check for RW1 else if (ch == 0xc0) { RW1_Start_byte_flag = 1; RW1_ReceivedCount = 0; RW1_Buffer[RW1_ReceivedCount++] = ch; // Note the cpu time when first character is received XTime_GetTime(&t_start_RW1); RW1_Frame_complete_flag = 0; } } if(RW1_Frame_complete_flag == 0) { // set up the buffer for next char in interrupt mode XUartNs550_Recv(&RW1, RW1_RecieveBuffer, 1); } } Thanks & Regards Ajeeth Kumar
  19. birca123


    Hello, I have a problem with the HDMI-IN example for ZYBO. As an input, I'm using FPV camera which has an analog output, and between the camera and ZYBO is AV2HDMI converter, which upscales NTSC resolution to 1080p or 720p HDMI signal. The problem is that ZYBO says that video capture resolution is 3996x5 when the output resolution from the converter is 720p and 3996x0 when the output resolution is 1080p. When I connect the camera to the TV as HDMI source, everything works perfectly. Is this solvable? Or should I use another HDMI source for this example? Best regards, Toni Birka
  20. Hi, I am working on a project where i'm using Digilent zybo AP SoC with xilinx vivado for Hardware design and Xilinx SDK for software design. My application uses following protocol/peripherals: 1. UARTns16550 PL side (Programmable Logic) in interrupt mode. 2. GPIOs 3. Ethernet mac (lwIP stack) I started my software design using xilinx lwip perf client application project. Then i started modifying the perf client C code according to my need. My project contains Uartns16550, tcp/ip server and client program which receives real-time data. So coming to my problem, i am able to run my application from xilinx sdk GDB and system debugger. But, when i dump my code in QSPI flash and try to boot, the zybo is not booting up. I also tried loading different application project like tcp perf server, perf client. By doing this the processor boots up properly through QSPI flash. I followed the steps provided by Digilent for programming the flash and i also ensured that the jumpers are in the right place where it has to be. I believe that there's a problem with my program since i have started modifying the tcp perf client code for my project. I am not getting a clue where my code is going wrong. Operating System : Windows 10 Software : Xilinx vivado 2018.3/SDK 2018.3 Any inputs related to this will be appreciated. Thanks & Regards Ajeeth kumar
  21. I want to use GNU RADIO to design an RF signal receiving circuit. For this I plan to use an FPGA card in the baseband section of the circuit (to handle the decimation and, if possible, to convert analogue to digital signal). My doubt lies in knowing if it is possible to communicate the FPGA card to the GNU RADIO application directly or if necessary from an external program. At this point it should be noted that I work in windows 10. I'm quite new on the subject of FPGA and GNU RADIO. I would really be grateful if you help me with this problem. The card is a Xilinx Zynq-7000 Developmet Board, the Z-7010, its features are best seen on the next page Suggestions for design changes are welcome. In advance thanks for the help.
  22. Any & all help is appreciated with this thread. I am 100% new rookie to FPGA. I purchased the Digilent Zybo Z7: Zynq-7000 ARM/FPGA SoC Development Board (Zybo Z7-20 with SDSoC Voucher) My intentions are to crypto currency mine a new FPGA algo called Odocrypt created by the blockchain group Digibyte DGB. Here are a couple links to the info. DigiByteCoin Github Odocrypt Mining Software It will change every 10 days. Its supposed to, to make it more ASIC resistant. I thought this may make a nice marketing tool also that is profitable & I'll gladly promote if someone can tell me how to set it up! Any input, insight or suggestions how to setup the Xilinx software for this particular FPGA to mine that Odocrypt algo on that mining pool... would be greatly appreciated! TYIA
  23. Hi, I am trying to interface XADC on Zybo with xillyubus to measure external analog values.Rest of the design is working okay with a counter.My Question is how do i connect XADC with the xillybus Ip Core. any help is appreciated thank you
  24. Hello, I am a college student currently working on the HDMI Input demo for the Zybo board on Vivado 2018.3 and SDK. I am following the steps provided on this forum, but I end up with trouble displaying the HDMI source onto the monitor. Without any modification, I can get the HDMI source to display properly; however, there seems to be many errors and warnings. In addition, modifying the C code by commenting out some of the switch statements resulted in no change whatsoever. After creating a new bsp and application project, followed by copy and pasting all of the source files, I had no errors popping up. I was able to see the results of the modifications I made, but the HDMI source wouldn't display onto the monitor (just the DemoPrintTest shows up). I have posted my project onto this link. If possible, I would like to get help on this matter.