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Since you folks an Digilent make these wonderful board files that make it super easy to connect components, I figured I'd make my own for a custom board. The problem is that my design uses a differential sysclock, whereas most Digilent designs use a single-ended sysclock. I have been pouring over the board file chapter in UG895 to figure out how to do this, but unfortunately I haven't found any examples or hints in doing so. A single-ended clock interface in the board.xml file looks like this: <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_
I was attempting to use the Board tab within a block design in Vivado 2016.4 to connect some of the board interfaces on a Nexys Video FPGA board. In particular, the HDMI In component goes and instantiates both the TMDS signals in, as well as the DDC signals out, and Vivado marks the HDMI In component as connected. However, when I go to synthesize or elaborate the design, I get a bunch of messages telling me that top-level ports have not been assigned to an IO, and if I open up the I/O Port window, I can see that there's no package pin assigned to the HDMI ports. The only package pins that seem