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Found 67 results

  1. Tomar

    ARTY question

    Hi, I was wondering if it is right place to ask questions about Arty board. Thanks Tomar
  2. Takeways: 1. Maximize the usage of the Xilinx Zynq 7000 resources 2. Understand the nuances and internal workings of the Xilinx Zynq 7000 3. Trade-off performance vs. energy consumption Complexity of systems implemented using FPGA's are exponentially growing in a rapid pace. As a result of it most of the common design issues that a designer come across with ASIC SoC are becoming relevant with FPGA as well. If we consider Xilinx Zynq 7000 Programmable SoC, there is considerable processing power on the compute side. A simple migration is insufficient to achieve the same performance as discrete chips and also achieving performance and implementation benefits of such a complex FPGA would be very less. Estimating or identification of system performance and crucial bottlenecks much before writing RTL not just reduces the development time but also increases the Quality of Results. During this event we will be talking about how performance analysis and architecture exploration of a Zynq 7000 based System in the early stage of system development ensures that the right FPGA platform is selected and achieves optimal partitioning of the application onto the fabric. To Register, Click here
  3. Hi, I would like to use the MicroBlaze performance monitoring engine to collect some information on my application code running on the processor itself. I would need these information at application level. I have a problem to access these values. In order to do these things, I have created a project with MicroBlaze and extended debug function, with 5 event counters and 1 latency counter. Then I have inserted a MDM in my design and created an AXI4lite slave port to access from MicroBlaze itself. In this mode I should be able to access to internal performance monitoring engine by using DBG_CTRL and DBG_DATA registers indicated to page 12 of pg115 (MDM product guide), with values indicated on page 92 of MB reference guide (version 2015.04). Suppose I need to measure number of any valid executed instruction, I have written the code attached to this post. The problem happens when I perform the read from *dbg_data: the read action on this variable does not give any response. The register pointed by variable is R/W. Do you have any suggestion about this wrong behaviour? Thank you. code.c
  4. How to setup diligent usb cable for Xilinx Spartan-3 starter kit on CentOS 6? I have already installed ISE WebPack, digilent.adept.runtime, digilent.adept.utilities, libCseDigilent, fxload, and some other packages. lsusb shows: [lukasz@localhost home]$ lsusb Bus 001 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub Bus 001 Device 006: ID 03fd:000d Xilinx, Inc. but djtgcfg shows nothing: sudo djtgcfg enum No devices found iMPACT log: Welcome to iMPACT iMPACT Version: 14.7 Project: /home/lukasz/VHDL/QLIW//auto_project.ipf created. // *** BATCH CMD : setMode -bs // *** BATCH CMD : setMode -bs // *** BATCH CMD : setMode -bs // *** BATCH CMD : setMode -bs GUI --- Auto connect to cable... // *** BATCH CMD : setCable -port auto INFO:iMPACT - Digilent Plugin: Plugin Version: 2.4.4 INFO:iMPACT - Digilent Plugin: no JTAG device was found. AutoDetecting cable. Please wait. *** WARNING ***: When port is set to auto detect mode, cable speed is set to default 6 MHz regardless of explicit arguments supplied for setting the baud rates PROGRESS_START - Starting Operation. If you are using the Platform Cable USB, please refer to the USB Cable Installation Guide (UG344) to install the libusb package. Connecting to cable (Usb Port - USB21). Checking cable driver. File version of /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusbdfwu.hex = 1030. File version of /etc/hotplug/usb/xusbdfwu.fw/xusbdfwu.hex = 1030. WinDriver v10.31 Jungo (c) 1997 - 2011 Build Date: May 24 2011 x86_64 64bit 18:13:19. Cable connection failed. Connecting to cable (Parallel Port - parport0). WinDriver v10.31 Jungo (c) 1997 - 2011 Build Date: May 24 2011 x86_64 64bit 18:13:19. Cable connection failed. Connecting to cable (Parallel Port - parport1). WinDriver v10.31 Jungo (c) 1997 - 2011 Build Date: May 24 2011 x86_64 64bit 18:13:19. Cable connection failed. Connecting to cable (Parallel Port - parport2). WinDriver v10.31 Jungo (c) 1997 - 2011 Build Date: May 24 2011 x86_64 64bit 18:13:19. Cable connection failed. Connecting to cable (Parallel Port - parport3). WinDriver v10.31 Jungo (c) 1997 - 2011 Build Date: May 24 2011 x86_64 64bit 18:13:19. Cable connection failed. PROGRESS_END - End Operation. Elapsed time = 2 sec. Cable autodetection failed. WARNING:iMPACT:923 - Can not find cable, check cable setup !
  5. Jaiko007

    3 bit output

    Hello, I need to design 3 bit output, which are 000, 001, 010, 011, 100 using FPGA. I'm using VHDL language. I have already designed it. But, the problem is I can't get that desired output I want. I got 000, 001, 011 and 111 outputs. Here I attach my code and testbench and also Isim simulator waveform part. Thank you. selectsig.vhd selectsig_tb.vhd simulator.wcfg
  6. Jaiko007

    8x1 multiplexer

    Hello, I want to design 8x1 multiplexer using FPGA. But, I just only have 5 options of input, which are freq1, freq2, freq3, freq4, and freq5. Is it possible to design it with only just have 5 options of input? If possible, how doing it? I'm using Xilinx and the language I used is VHDL. Here I attach a picture. Please help me. Thank you.
  7. Jaiko007

    MUX 2x1 using VHDL

    Hello, I need to design PWM for a multiplexer 2x1 for my project. The description is: If select = 0, output = input 1 (10kHz) If select = 1, output = input 2 (100kHz) The problem is, I don't know how to implement that frequency in my coding. Is it possible to do that. If yes, how making it? Someone please help me. Here, I attach my code. mux2to1.vhd mux2to1_tb.vhd Thank you.
  8. Hello, I need to design frequency divider from 50MHz to 200Hz using FPGA. I'm using Xilinx and the language that I used is VHDL language. I got stuck because I can't get the output. So, anyone can help me? This is for the code,FreqDivider.vhd and this is for testbench, FreqDivider_tb.vhd. Thanks.
  9. I ran speech simulation (analog) on Matlab, and here is the code and result. I want create an analog stimulus file for UNISIM for XADC execution on Xilinx Vivado. I use Vivado 2015.4 with board Artix7 (xc7t35cpg236 - 1C). 1. How to make an analog stimulus file using these information? I will need Time(ns), VAUXP(V), TEMP, VCCINT, VCCAUX, VCCBRAM values. 2. How many set of readings can I take? 3. Should the time be in millisecond, nanoseconds or seconds? Please find attached 'SIM_MONITOR_FILE' saved in data.xls and the simulation file for word 'Jam', obtained using Matlab 'audiorecorder'. data.xls
  10. Twoism

    Zybo base system design

    Hello, I've got some troubles while trying to fully understand the Zybo base system design. I need to replicate in my design (with Vivado 2015.4) the video part of the bsd, with the Axi display control ip. The design works but some points are not very clear to me: I've notice that 2 different clock sources are feed to the PL: (FCLK_CLK0 @ 100 MHz and FCLK_CLK1 @ 150 MHz). What is the reason behind this? Isn't 100 MHz enough for the VDMA? Why an Axi protocol converter is used? The design was build for an older version of Vivado (and ip library)? Thanks
  11. Hi I have done an intro to vivado simulation in Verilog based on the assignment I have done in ISE http://m.instructables.com/id/How-to-Use-Vivado-Simluation/?ALLSTEPS
  12. What about Nexys4 BSP for EDK XPS wizard? I am using Xilinx 14.7 for Embedded Systems with tihis card and i cant find these suppor t files to use in wizard like other boards. Thanks in advance
  13. I have done this project for an online class. The project is written by Verilog. The clock divider and counter modules were provided. My task was to write the top module to display 3 bit output of the counter on the 7 segment display. Originally, the project was implemented in Basys 2. I also used Xilinx ISE Webpack. Now, I modified the counter module and top module and implemented it on Basys 3. In addition, I used Vivado Webpack instead of ISE. http://m.instructables.com/id/How-to-use-Verilog-and-Basys-3-to-do-3-bit-binary-/
  14. Hello Everyone, I need help determining whether the JTAG-HS2 is compatible with Xilinx Spartan XC3S400 FPGA JTAG. I'm brand new to Xilinx FPGA Thanks, Vu
  15. Hello, My team is trying to design a circuit with the Zybo board and we wished to power the circuit via an external battery and we were wondering what the maximum current & wattage allowance was. The datasheet specifies 5.5 Volts running through the board but nothing else.
  16. How can I set up a variable clock signal on Basys 2?
  17. A customer asks me the following question. I would like to share in the forum. Question: We want to know where we can find out documentation or media or resources? Answer: You can download the Xilinx Webpack and Impact at the xilinx.com. Regarding the documentation, you can go to the product webpage http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1000&Prod=CR2-STARTER. It has schematics, reference manual and a demo file.