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Found 65 results

  1. Hi, Can I use a CMOD A7 to run co-simulations using Vivado System Generator? In previous versions of System Generator it was possible to add custom boards. Is there a way to do it in Vivado?
  2. Dear all, I would like to buy JTAG HS2, but I have the followings doubts: 1. is it recognised by Fedora? 2. does it support debugging? 3. does it work with urJTAG? 4. is it compatible with openOCD? Thanks! gm
  3. Hello, I'm having trouble understanding how to address the J6 header on the Arty board. I've been able to interact with the GPIO registers to toggle other ChipKit shield pins as well as toggle all of the led's. When generating the project, I see that the base address for SPI in my project is at 0x44a00000 with high address being 0x44a0FFFF. I don't understand where in that memory the J6 header is, and am unable to find any resources with the answer. It might also be good to note that I generated the IP block by dragging and dropping the "SPI connector J6" from the Board section of the IP design. I've looked into the implemented design and see that the spi_io0_io, spi_io1_io, spi_ss_io, and spi_sck_io are connected correctly according to the arty schematic, I'm just unsure how to do SPI transfers over these pins (my logic analyzer doesn't show any activity when doing transfers). Regards, Nystflame
  4. Hi, I am trying to rebuild the arty z7 petalinux BSP as per the instructions given by them here https://github.com/Digilent/petalinux-bsps/wiki/Quick-Start-Guide-for-Arty-Z7. But when I try the command $ petalinux-boot --jtag --prebuilt 3, I get an error saying [skaat27@localhost Digilent-Arty-Z7-Linux-BD-v2016.2]$ petalinux-boot --jtag --prebuilt 3 ERROR: No subsystem configuration file can be find in the project. sh: lsb_release: command not found webtalk failed:Invalid tool in the statistics file:petalinux-yocto! webtalk failed:Failed to get PetaLinux usage statistics! Anybody knows what the issue is? Karthik
  5. I have a Z-Turn FPGA, based around a Xilinx Zynq 7020. Unfortunately, its JTAG port is 2x7 with 2.54mm pitch. I just realized the HS3 uses 2.00mm pitch. Is there a recommended way to convert the pin pitch? I designed my own board, but an existing option would be more convenient.
  6. Hi - I just tried to install the XUP USB-JTAG Programming Cable from diligent. I also have a Diligent Programming Cable. Centos can see both cables (see below) Vivado can see the Diligent programming cable but not the Xilinx one. Given the physical constraints of the installation only the Xilinx one will work. Are there any specific instructions to get the Xilinx cable going? $lsusb | grep "Xilinx/|Future" Bus 002 Device 003: ID 03fd:000d Xilinx, Inc. Bus 001 Device 006: ID 0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC
  7. Hello, im new on this forum. Im trying to learn how to use a extern DDR2 RAM that my Virtex 5 have. I honestly dont know the step by step. I do this to learn how to use the FPGA in order to gaining experience for a future proyect. The most difficult module that i used was the Display and works fine. Im using ISE 14.7 With the DDR2 RAM the only thing i did was creating the file that Core Generator Tool provides after the first configuration. I had a problem there: i couldnt assign all the ports but i was able to create the file anyway. Now i'm not shure what to do next. I'd apreciate any help that someone can provide or some tip to follow. Sorry but im a little lost in this subject. I have a Virtex 5, XC5VLX50T. Thank you!
  8. I have the sample constraint file for my Arty board. I notice that where it says a clock signal is created in the file, it specifies a specific port that the clock is found on, specifically PACKAGE_PIN E3. set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}]; This creates a 100 MHz clock for the Arty. However, my current project needs a 20 MHz clock. I lack the FPGA knowledge to know whether these two lines of code are *describing* a clock that already exists at E3 on the Verilog board, or *creating* it. The "create clock" implies that it's creating, but the way the rest of the constraint file is formatted - with a list of the pins that exist on the Arty and their locations - suggests that it's only describing. Is it safe or even possible to make a 20 MHz clock by simply changing the number after -period to 50.00 for a 50 ns 20 MHz clock? Is there a way I can also keep the 100 MHz clock at the same time?
  9. WTB!!! in need of any / all Working Digilent Xilinx Virtex 5 FPGA boards for a company project! paying "cash" via paypal!!! pls PM me if you have a Genesys Virtex 5 board in 100% working order that you want to ditch, upgrade, or need cash. Thanks! -H
  10. Carson

    Xilinx FPGA Spartan 6

    Hi, I'm currently developing an embedded system using an FPGA board, which has an embedded Digilent USB JTAG programmer that enables the FPGA to be configured via the USB port on the PCIe bus. I’m trying to figure out how to use the Digilent linux configuration program “djtgcfg” to program a .bit file into the FPGA but noticed that it is not able to properly identify the Xilinx Spartan 6 chip (pn XC6SLX45T) on the board. I think the program is not able to find the Spartan device on a file “jtscdvclist.txt”, which is a lookup file containing a lot of Xilinx parts. However, I am not able to see the XC6SLX45T on the list. The closest that I could find was the XC6SLX (without the T on the end) on that list. BTW, I also see this problem when I use the Xilinx ISE impact tool plugin. Does Digilent support this particular Xilinx chip? [carsonmurray@CRS_Server_devpc104 bin64]$ ./djtgcfg init -d RTD16850149 Initializing scan chain... Found Device ID: 44028093 Found Device ID: d5058093 Found 2 device(s): Device 0: XCF16P Device 1: XC6SLX ? XILINX{ FAMILY{ ;--- FPGAs XC2S$ 00600000h 0FE00000h XC2S$E 00A00000h 0FE00000h XC3S$ 01400000h 0FE00000h XC3SD$A 06800000h 0FE00000h XC3S$AN 02600000h 0FE00000h XC3S$A 02200000h 0FE00000h XC3S$E 01C00000h 0FE00000h XC6SLX$ 04000000h 0FE00000h XC7A$T 03620000h 0FFF0000h XC7A$T 03630000h 0FFF0000h XC7K$T 03640000h 0FEE0000h XC7VX$T 03660000h 0FFF0000h XC7VX$T 03680000h 0FFE0000h XC7Z$ 03700000h 0FF00000h XCV$ 00600000h 0FE00000h XCV$E 00A00000h 0FE00000h XC2V$ 01000000h 0FE00000h XC2VP$ 01200000h 0FE00000h XC4VFX$ 01E00000h 0FE00000h XC4VLX$ 01600000h 0FE00000h XC4VSX$ 02000000h 0FE00000h XC5VFX$T 03200000h 0FE00000h XC5VLX$ 02800000h 0FE00000h XC5VLX$T 02a00000h 0FE00000h XC5VSX$T 02e00000h 0FE00000h XC5VTX$T 04500000h 0FE00000h XC6VCX$T 042c0000h 0FFE0000h XC6VLX$T 04240000h 0FFE0000h XC6VLX760T 04230000h 0FFF0000h XC6VSX$T 04280000h 0FFE0000h XC6SLX${ TYPE = FPGA IRLEN = 6 ALG = 5 COMMANDS{ CFG_OUT 00000004h ;---000100 IDCODE 00000009h ;---001001 CFG_IN 00000005h ;---000101 JSTART 0000000Ch ;---001100 BYPASS 0000003Fh ;---111111 JPROGRAM 0000000Bh ;---001011 JSHUTDOWN 0000000Dh ;---001101 } DEVICES{ 4 04000093h 0FFFFFFFh 16 04002093h 0FFFFFFFh 25 04004093h 0FFFFFFFh 45 04008093h 0FFFFFFFh 150 0401D093h 0FFFFFFFh } } Thanks, Carson
  11. Hi, I'm using Digilent's XUP USB-JTAG Programming Cable to program 'Z-turn board' which uses Xilinx Zynq-7000(http://www.myirtech.com/list.asp?id=502). There was no problem when I programed Bitstream or BBRAM through JTAG, but when I tried to program eFUSE Xilinx Vivado threw an error - ERROR: [Labtools 27-3277] jsn-DLC9LP-00000000000000 cable is not supported for EFUSE programming. Please use a Xilinx PCUSB2 DLC10 or approved Digilent cable I think my cable is approved one. Does anyone have any solution for this? Thank you in advance.
  12. Dear sir, I am using xilinx FFT 9.0 IP core in Vivado 15.2 for my application, I am computing 512 point IFFT with cyclic prefix using this IP core but output is not coming correctly. Although most of the output samples are correct but some samples are changing drastically. I am using this IP core in real time mode and giving 512 complex symbol at the input of core on every clock after s_axis_data_tvalid and s_axis_data_tready becomes high. Earlier I have used xilinx FFT 7.1 IP core in ISE14.6 which working fine with same settings and same input data. Kindly help me to debug this IP core
  13. When I click Vivado License Manager to activate the Vivado Design Tools license, I am met with a window asking me to either "repair", or "uninstall" Microsoft 2012 C++ redistrobutables. It doesn't matter if I repair, I get the same message next time. If I uninstall I get the message asking for the installation of the same Microsoft C++ package. If I install it the next time I click on VLM I get the same error. Does anyone know how to work around this problem? Iv included my Xilinx install log. Im sort of new to FPGA development, any help is greatly appreciated. xinstall.log
  14. Good afternoon I am learning to use VHDL. I have a Nexys 4 ddr and a PmodSD card, that I would like to learn to use. I downloaded the most recent version of VIVADO, and Xilinx as well. Do you all have a program that I can use, to see how it works or a tutorial to process images? I would appreciate it. Thank you. Kind regards.
  15. Hi , I have a question with the PMOD . I am using ZYNQ 706 board PMOD ports to connect to my fabric (PL) . I have pin locs in place for the PMOD which is connected to the JTAG singals of the ARC processor. I have attached the board setup. djtgcfg enum. Device: JtagHs2 Product Name: Digilent JTAG-HS2 User Name: JtagHs2 Serial Number: 210249A05F4C Before programming the bit file even with the board turned off. djtgcfg init -d JtagHs2. [piyerlab1]$ djtgcfg init -d JtagHs2 Initializing scan chain... Found 0 device(s): When i turn on the board without bit file. [piyerlab1 ~]$ djtgcfg init -d JtagHs2 --verbose Initializing scan chain... ERROR: failed to initialize scan chain Received error: init failed Again With board turned on and bit file programmed , [piyerlab1]$ djtgcfg init -d JtagHs2 Initializing scan chain... Found 0 device(s): I don't know how debug this. I don't know why my arc jtag chain is not detected. I am connected to the PMOD J58 of the ZYNQ 706 board. This PMOD pin is connected to my ARC processor JTAG pins. Please advice how to debug. Regards, Prashanth
  16. Hi, I am using Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit and I am newbie for using this board. I'm following this link to generate an interrupt using GPIO switches and turn off a led : http://www.wiki.xilinx.com/Linux+GPIO+Driver. The drivers works correctly and the led is heartbeating, when i check /proc/interrupts i get: ... 223: 0 0 0 0 GICv2 154 Level fd4c0000.dma 224: 0 0 0 0 xgpio 0 Edge sw14 233: 0 0 0 0 GICv2 97 Level xhci-hcd:usb1 ... but when i switch on cpu stops and i get this error: root@Xilinx-ZCU102-2016_1:~# [ 18.111391] Unable to handle kernel paging request at virtual address b9410a80aa13043f [ 18.119243] pgd = ffffffc87ad07000 [ 18.122615] [b9410a80aa13043f] *pgd=0000000000000000, *pud=0000000000000000 [ 18.129559] Internal error: Oops: 96000004 [#1] SMP [ 18.134420] Modules linked in: [ 18.137460] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.4.0 #78 [ 18.143361] Hardware name: ZynqMP ZCU102 RevB (DT) [ 18.148136] task: ffffffc00224efc0 ti: ffffffc002240000 task.ti: ffffffc002240000 [ 18.155613] PC is at xgpio_irqhandler+0x2c/0x144 [ 18.160202] LR is at xgpio_irqhandler+0x1c/0x144 [ 18.164801] pc : [<ffffffc0003c8ee0>] lr : [<ffffffc0003c8ed0>] pstate: 600001c5 [ 18.172185] sp : ffffffc002243d00 [ 18.175476] x29: ffffffc002243d00 x28: 0000000000000000 [ 18.180769] x27: 0000000000000000 x26: ffffffc0022c2000 [ 18.186063] x25: ffffffc00078acf0 x24: ffffff8000015000 [ 18.191358] x23: ffffffc0003c8eb4 x22: b9410a80aa1303f7 [ 18.196653] x21: 0000000000000000 x20: 0000000000000000 [ 18.201948] x19: ffffffc002227000 x18: 0000000000000001 [ 18.207242] x17: 0000000000000006 x16: ffffffbe1dae9f68 [ 18.212537] x15: ffffffc87b08f000 x14: 0000000000000007 [ 18.217832] x13: ffffffc87b801128 x12: 0000004000000000 [ 18.223127] x11: ffffffc002246000 x10: 00000000000006e0 [ 18.228422] x9 : ffffffc002243e70 x8 : ffffffc87b400058 [ 18.233716] x7 : ffffffc87b400d88 x6 : 0000000000000002 [ 18.239011] x5 : 00000000fffffffa x4 : ffffffc87b400d89 [ 18.244306] x3 : 0000000000000000 x2 : 0000000000000000 [ 18.249601] x1 : 0000000000000020 x0 : 0000000000000000 [ 18.254895] [ 18.256373] Process swapper/0 (pid: 0, stack limit = 0xffffffc002240020) [ 18.263060] Stack: (0xffffffc002243d00 to 0xffffffc002244000) [ 18.268790] 3d00: ffffffc002243d50 ffffffc0000d1088 ffffffc002227000 0000000000000000 [ 18.276609] 3d20: 0000000000000000 ffffffc002249040 ffffff8000014010 ffffffc0000d13cc [ 18.284421] 3d40: ffffffc002243d50 ffffffc0000d107c ffffffc002243d60 ffffffc0000d13a0 [ 18.292232] 3d60: ffffffc002243da0 ffffffc000080cec ffffff800001400c ffffffc002279000 [ 18.300045] 3d80: ffffffc002243de0 ffffffc0000e5ed0 ffffffc87b808000 00000079000ec410 [ 18.307857] 3da0: ffffffc002243f00 ffffffc000083da8 ffffffc002240000 ffffffc002246000 [ 18.315668] 3dc0: ffffffc002243f00 ffffffc000084e70 0000000060000145 ffffffc002228f40 [ 18.323480] 3de0: 0000000000000000 0000000000000000 0000000000000001 0000000000000000 [ 18.331292] 3e00: 0000000000000000 000000001999999a 002aad4b00000000 00000000fffeecaa [ 18.339104] 3e20: 00000000fffeecab ffffffc002243e70 00000000000006e0 ffffffc002246000 [ 18.346916] 3e40: 0000004000000000 ffffffc87b801128 0000000000000007 ffffffc87b08f000 [ 18.354729] 3e60: ffffffbe1dae9f68 0000000000000006 0000000000000001 ffffffc002240000 [ 18.362541] 3e80: ffffffc002246000 ffffffc002246ad0 ffffffc0022259c0 ffffffc002243f20 [ 18.370352] 3ea0: ffffffc002228f40 ffffffc00078acf0 ffffffc0022c2000 0000000000000000 [ 18.378164] 3ec0: 0000000000000000 ffffffc002243f00 ffffffc000084e6c ffffffc002243f00 [ 18.385977] 3ee0: ffffffc000084e70 0000000060000145 ffffffc00078acf0 ffffffc00077c278 [ 18.393789] 3f00: ffffffc002243f10 ffffffc0000ca2e0 ffffffc002243f20 ffffffc0000ca418 [ 18.401600] 3f20: ffffffc002243f90 ffffffc000779080 ffffffc0022c5000 ffffffc0022c5000 [ 18.409413] 3f40: ffffffc0022c5000 ffffffc002246000 ffffffc87ffa2580 ffffffc000a6fca8 [ 18.417224] 3f60: 000000000231c000 000000000231f000 ffffffc0000801d8 0000000000000000 [ 18.425037] 3f80: ffffffc002243f90 ffffffc000779078 ffffffc002243fa0 ffffffc000a3d94c [ 18.432848] 3fa0: 0000000000000000 0000000000780000 0000000000000000 0000000000000e12 [ 18.440660] 3fc0: 0000000004080000 0000000000000000 0000000000000000 0000000000000000 [ 18.448472] 3fe0: 0000000000000000 ffffffc000a6fca8 0000000000000000 0000000000000000 [ 18.456281] Call trace: [ 18.458707] [<ffffffc0003c8ee0>] xgpio_irqhandler+0x2c/0x144 [ 18.464353] [<ffffffc0000d1088>] generic_handle_irq+0x24/0x38 [ 18.470079] [<ffffffc0000d13a0>] __handle_domain_irq+0x60/0xac [ 18.475895] [<ffffffc000080cec>] gic_handle_irq+0x60/0xb4 [ 18.481274] Exception stack(0xffffffc002243db0 to 0xffffffc002243ed0) [ 18.487699] 3da0: ffffffc002240000 ffffffc002246000 [ 18.495518] 3dc0: ffffffc002243f00 ffffffc000084e70 0000000060000145 ffffffc002228f40 [ 18.503329] 3de0: 0000000000000000 0000000000000000 0000000000000001 0000000000000000 [ 18.511142] 3e00: 0000000000000000 000000001999999a 002aad4b00000000 00000000fffeecaa [ 18.518954] 3e20: 00000000fffeecab ffffffc002243e70 00000000000006e0 ffffffc002246000 [ 18.526766] 3e40: 0000004000000000 ffffffc87b801128 0000000000000007 ffffffc87b08f000 [ 18.534578] 3e60: ffffffbe1dae9f68 0000000000000006 0000000000000001 ffffffc002240000 [ 18.542390] 3e80: ffffffc002246000 ffffffc002246ad0 ffffffc0022259c0 ffffffc002243f20 [ 18.550202] 3ea0: ffffffc002228f40 ffffffc00078acf0 ffffffc0022c2000 0000000000000000 [ 18.558013] 3ec0: 0000000000000000 ffffffc002243f00 [ 18.562868] [<ffffffc000083da8>] el1_irq+0x68/0xc0 [ 18.567643] [<ffffffc0000ca2e0>] default_idle_call+0x1c/0x30 [ 18.573284] [<ffffffc0000ca418>] cpu_startup_entry+0x124/0x1dc [ 18.579101] [<ffffffc000779080>] rest_init+0x74/0x7c [ 18.584049] [<ffffffc000a3d94c>] start_kernel+0x394/0x3a8 [ 18.589427] [<0000000000780000>] 0x780000 [ 18.593421] Code: b4000820 f9400800 f9400414 f9401ef6 (f94026c0) [ 18.599503] ---[ end trace fc72e20977be1640 ]--- [ 18.604096] Kernel panic - not syncing: Fatal exception in interrupt [ 18.610435] CPU3: stopping [ 18.613125] CPU: 3 PID: 0 Comm: swapper/3 Tainted: G D 4.4.0 #78 [ 18.620241] Hardware name: ZynqMP ZCU102 RevB (DT) [ 18.625013] Call trace: [ 18.627447] [<ffffffc000087da8>] dump_backtrace+0x0/0x114 [ 18.632829] [<ffffffc000087ed0>] show_stack+0x14/0x1c [ 18.637865] [<ffffffc000393cf8>] dump_stack+0x84/0xa0 [ 18.642897] [<ffffffc00008d4cc>] handle_IPI+0x18c/0x1a0 [ 18.648104] [<ffffffc000080d28>] gic_handle_irq+0x9c/0xb4 [ 18.653486] Exception stack(0xffffffc87b8efdf0 to 0xffffffc87b8eff10) [ 18.659910] fde0: ffffffc87b8ec000 ffffffc002246000 [ 18.667730] fe00: ffffffc87b8eff40 ffffffc000084e70 0000000060000145 ffffffc002228f40 [ 18.675541] fe20: 0000000000000000 0000000000000000 0000000000000001 0000000000000000 [ 18.683353] fe40: 0000000000000000 000000001999999a 000a037a00000000 00000000fffeed1b [ 18.691165] fe60: 00000000fffeed1c ffffffc87b8efeb0 00000000000006e0 0000000000000005 [ 18.698977] fe80: ffffffc00078b5d4 ffffffc073ad7b80 ffffffc87b325380 ffffffc87ba30000 [ 18.706789] fea0: ffffffbe1db0baa0 0000000000000006 0000000000000001 ffffffc87b8ec000 [ 18.714601] fec0: ffffffc002246000 ffffffc002246ad0 ffffffc0022259c0 ffffffc87b8eff60 [ 18.722413] fee0: ffffffc002228f40 ffffffc00078acf0 ffffffc0022c2000 0000000000000000 [ 18.730224] ff00: 0000000000000000 ffffffc87b8eff40 [ 18.735078] [<ffffffc000083da8>] el1_irq+0x68/0xc0 [ 18.739853] [<ffffffc0000ca2e0>] default_idle_call+0x1c/0x30 [ 18.745496] [<ffffffc0000ca418>] cpu_startup_entry+0x124/0x1dc [ 18.751310] [<ffffffc00008cfcc>] secondary_start_kernel+0x11c/0x140 [ 18.757559] [<000000000008103c>] 0x8103c [ 18.761464] CPU2: stopping [ 18.764157] CPU: 2 PID: 0 Comm: swapper/2 Tainted: G D 4.4.0 #78 [ 18.771273] Hardware name: ZynqMP ZCU102 RevB (DT) [ 18.776045] Call trace: [ 18.778479] [<ffffffc000087da8>] dump_backtrace+0x0/0x114 [ 18.783861] [<ffffffc000087ed0>] show_stack+0x14/0x1c [ 18.788895] [<ffffffc000393cf8>] dump_stack+0x84/0xa0 [ 18.793929] [<ffffffc00008d4cc>] handle_IPI+0x18c/0x1a0 [ 18.799136] [<ffffffc000080d28>] gic_handle_irq+0x9c/0xb4 [ 18.804518] Exception stack(0xffffffc87b8ebdf0 to 0xffffffc87b8ebf10) [ 18.810942] bde0: ffffffc87b8e8000 ffffffc002246000 [ 18.818762] be00: ffffffc87b8ebf40 ffffffc000084e70 0000000060000145 ffffffc002228f40 [ 18.826573] be20: 0000000000000000 0000000000000000 0000000000000001 0000000000000000 [ 18.834385] be40: 0000000000000000 000000001999999a 000f424000000000 00000000fffeed31 [ 18.842197] be60: 00000000fffeed32 ffffffc87b8ebeb0 00000000000006e0 ffffffc002246000 [ 18.850009] be80: 0000004000000000 ffffffc87b801128 000000000000001c ffffffc87ac9c000 [ 18.857821] bea0: ffffffbe1dadc240 0000000000000006 0000000000000001 ffffffc87b8e8000 [ 18.865633] bec0: ffffffc002246000 ffffffc002246ad0 ffffffc0022259c0 ffffffc87b8ebf60 [ 18.873445] bee0: ffffffc002228f40 ffffffc00078acf0 ffffffc0022c2000 0000000000000000 [ 18.881256] bf00: 0000000000000000 ffffffc87b8ebf40 [ 18.886110] [<ffffffc000083da8>] el1_irq+0x68/0xc0 [ 18.890885] [<ffffffc0000ca2e0>] default_idle_call+0x1c/0x30 [ 18.896527] [<ffffffc0000ca418>] cpu_startup_entry+0x124/0x1dc [ 18.902342] [<ffffffc00008cfcc>] secondary_start_kernel+0x11c/0x140 [ 18.908591] [<000000000008103c>] 0x8103c [ 18.912496] CPU1: stopping [ 18.915188] CPU: 1 PID: 0 Comm: swapper/1 Tainted: G D 4.4.0 #78 [ 18.922305] Hardware name: ZynqMP ZCU102 RevB (DT) [ 18.927077] Call trace: [ 18.929511] [<ffffffc000087da8>] dump_backtrace+0x0/0x114 [ 18.934893] [<ffffffc000087ed0>] show_stack+0x14/0x1c [ 18.939927] [<ffffffc000393cf8>] dump_stack+0x84/0xa0 [ 18.944961] [<ffffffc00008d4cc>] handle_IPI+0x18c/0x1a0 [ 18.950168] [<ffffffc000080d28>] gic_handle_irq+0x9c/0xb4 [ 18.955550] Exception stack(0xffffffc87b8e3df0 to 0xffffffc87b8e3f10) [ 18.961974] 3de0: ffffffc87b8e0000 ffffffc002246000 [ 18.969794] 3e00: ffffffc87b8e3f40 ffffffc000084e70 0000000060000145 ffffffc002228f40 [ 18.977605] 3e20: 0000000000000000 0000000000000000 0000000000000001 0000000000000000 [ 18.985417] 3e40: 0000000000000000 000000001999999a 000cdfe600000000 00000000fffeed27 [ 18.993229] 3e60: 00000000fffeed28 ffffffc87b8e3eb0 00000000000006e0 ffffffc002246000 [ 19.001041] 3e80: 0000004000000000 ffffffc87b801128 000000000000000e ffffffc87b3de000 [ 19.008853] 3ea0: ffffffbe1daf58b0 0000000000000006 0000000000000001 ffffffc87b8e0000 [ 19.016665] 3ec0: ffffffc002246000 ffffffc002246ad0 ffffffc0022259c0 ffffffc87b8e3f60 [ 19.024477] 3ee0: ffffffc002228f40 ffffffc00078acf0 ffffffc0022c2000 0000000000000000 [ 19.032288] 3f00: 0000000000000000 ffffffc87b8e3f40 [ 19.037142] [<ffffffc000083da8>] el1_irq+0x68/0xc0 [ 19.041917] [<ffffffc0000ca2e0>] default_idle_call+0x1c/0x30 [ 19.047559] [<ffffffc0000ca418>] cpu_startup_entry+0x124/0x1dc [ 19.053374] [<ffffffc00008cfcc>] secondary_start_kernel+0x11c/0x140 [ 19.059623] [<000000000008103c>] 0x8103c [ 19.063529] ---[ end Kernel panic - not syncing: Fatal exception in interrupt This is my pl.dtsi: / { amba_pl: amba_pl { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; ranges ; axi_gpio_0: gpio@80000000 { #gpio-cells = <2>; #interrupt-cells = <2>; compatible = "xlnx,xps-gpio-1.00.a"; gpio-controller ; interrupt-controller ; interrupt-parent = <&gic>; interrupts = <0 89 1>; reg = <0x0 0x80000000 0x0 0x10000>; xlnx,all-inputs = <0x1>; xlnx,all-inputs-2 = <0x0>; xlnx,all-outputs = <0x0>; xlnx,all-outputs-2 = <0x0>; xlnx,dout-default = <0x00000000>; xlnx,dout-default-2 = <0x00000000>; xlnx,gpio-width = <0x8>; xlnx,gpio2-width = <0x20>; xlnx,interrupt-present = <0x1>; xlnx,is-dual = <0x0>; xlnx,tri-default = <0xFFFFFFFF>; xlnx,tri-default-2 = <0xFFFFFFFF>; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw14 { label = "sw14"; gpios = <&axi_gpio_0 0 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; axi_gpio_1: gpio@80010000 { #gpio-cells = <2>; compatible = "xlnx,xps-gpio-1.00.a"; gpio-controller ; reg = <0x0 0x80010000 0x0 0x10000>; xlnx,all-inputs = <0x0>; xlnx,all-inputs-2 = <0x0>; xlnx,all-outputs = <0x1>; xlnx,all-outputs-2 = <0x0>; xlnx,dout-default = <0x00000000>; xlnx,dout-default-2 = <0x00000000>; xlnx,gpio-width = <0x8>; xlnx,gpio2-width = <0x20>; xlnx,interrupt-present = <0x0>; xlnx,is-dual = <0x0>; xlnx,tri-default = <0xFFFFFFFF>; xlnx,tri-default-2 = <0xFFFFFFFF>; }; gpio-leds { compatible = "gpio-leds"; led-ds23 { label = "led-ds23"; gpios = <&axi_gpio_1 0 0>; default-state = "on"; linux,default-trigger = "heartbeat"; }; }; }; };
  17. Hi, We're designing several boards that have a mixture of XIlinx Fpgas. One such board has multiple Virtex 5's, a Kintex 7 and a Spartan 6. We want to use a JTAG-SMT2 board to both configure the Fpgas and then use Chipscope for debugging. This means that all the Fpgas would be on a single JTAG chain. Has this been done before? Should a configuration like this work? We would be driving (via USB) the JTAG-SMT2 from an embedded linux processor and use the ADEPT SDK for configuration as well as implementing USB over Ethernet so that the Xilinx debug tools could run seamlessly on a laptop. Thanks Marc Howard
  18. Hi, Im trying to catch an interrupt from an AXI GPIO switch from my board ZCU102. I have created the following design in Vivado: The design is validated so now im using Petalinux to boot linux. I have exported the .hdf file and built petalinux but i can't boot linux.It hangs after that: Exit from FSBL NOTICE: ATF running on XCZU9EG/silicon v1/RTL5.1 at 0xfffe5000 NOTICE: BL31: Secure code at 0xfffc0000 NOTICE: BL31: Non secure code at 0x8000000 NOTICE: BL31: v1.2(release): NOTICE: BL31: Built : 17:17:47, Dec 1 2016 [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 4.4.0 (tecnobit@TBL241) (gcc version 4.9.2 20140904 (prerelease) (crosstool-NG linaro-1.13.1-4.9-2014.09 - Linaro GCC 4.9-2014.09) ) #2 SMP Thu Dec 1 17:19:05 CET 2016 [ 0.000000] Boot CPU: AArch64 Processor [410fd034] [ 0.000000] earlycon: Early serial console at MMIO 0xff000000 (options '115200n8') [ 0.000000] bootconsole [uart0] enabled [ 0.000000] cma: Reserved 128 MiB at 0x0000000078000000 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.0 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] PERCPU: Embedded 15 pages/cpu @ffffffc87ff71000 s23936 r8192 d29312 u61440 [ 0.000000] Detected VIPT I-cache on CPU0 [ 0.000000] CPU features: enabling workaround for ARM erratum 845719 [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 1034240 [ 0.000000] Kernel command line: earlycon=cdns,mmio,0xFF000000,115200n8 [ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) [ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes) [ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes) [ 0.000000] software IO TLB [mem 0x73fff000-0x77fff000] (64MB) mapped at [ffffffc073fff000-ffffffc077ffefff] [ 0.000000] Memory: 3908832K/4194304K available (7061K kernel code, 520K rwdata, 2692K rodata, 13604K init, 348K bss, 154400K reserved, 131072K cma-reserved) [ 0.000000] Virtual kernel memory layout: [ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbdffff0000 ( 247 GB) [ 0.000000] vmemmap : 0xffffffbe00000000 - 0xffffffbfc0000000 ( 7 GB maximum) [ 0.000000] 0xffffffbe00000000 - 0xffffffbe1dc00000 ( 476 MB actual) [ 0.000000] fixed : 0xffffffbffa7fd000 - 0xffffffbffac00000 ( 4108 KB) [ 0.000000] PCI I/O : 0xffffffbffae00000 - 0xffffffbffbe00000 ( 16 MB) [ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB) [ 0.000000] memory : 0xffffffc000000000 - 0xffffffc880000000 ( 34816 MB) [ 0.000000] .init : 0xffffffc000a07000 - 0xffffffc001750000 ( 13604 KB) [ 0.000000] .text : 0xffffffc000080000 - 0xffffffc000a06ff4 ( 9756 KB) [ 0.000000] .data : 0xffffffc001762000 - 0xffffffc0017e4360 ( 521 KB) [ 0.000000] Hierarchical RCU implementation. [ 0.000000] Build-time adjustment of leaf fanout to 64. [ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4. [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=4 [ 0.000000] NR_IRQS:64 nr_irqs:64 0 [ 0.000000] GIC: Using split EOI/Deactivate mode [ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys). [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns [ 0.000003] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns [ 0.008316] Console: colour dummy device 80x25 [ 0.012575] console [tty0] enabled [ 0.015942] bootconsole [uart0] disabled If i boot petalinux by qemu i manage boot linux, but the interrupt i defined in the design does not appear on the system I'm beggining with embedded linux so i don't know if i'm missing something. Any idea?? pl.dtsi zynqmp.dtsi pcw.dtsi system-top.dts system-conf.dtsi
  19. Hi all, I am currently doing the Xilinx tutorial to run Linux on my zybo : http://www.wiki.xilinx.com/Build+FSBL In the process, I have to get these task done : Bitstream (for the programmable logic portion) System hardware project hdf file My question is : can I use the https://reference.digilentinc.com/_media/zybo/zybo_base_system.zip ...to generate the bitstream and the system hardware project ? If I complete the tutorial with the generated files, will I be able to run linux and use it with the hdmi or vga output, get access to any kind of command prompt? Thanks. Regards, Herrmattoon
  20. Dr. Lizy Kurian John from University of Texas at Austin shared the lab manual for EE 460 Digital Systems using Verilog at http://users.ece.utexas.edu/~ljohn/teaching/ee460m_lab_manual.pdf
  21. Hello everyone; I am trying to boot Linux on Zybo using this tutorial: http://www.instructables.com/id/Embedded-Linux-Tutorial-Zybo/?ALLSTEPS I have load Boot,bin, devicetree.dtb uImage and uramdisk.image intor fat32 partition of my 16 Gb sd card. size of uramdisk.image is around 5 Mb. when I boot the Linux, I have the problem like this, BAD DATA CRC h Do you have any experience on that ? is the size of kernel correct?
  22. Hello, How to generate a variable duty cycle from this code? This code is for 10% duty cycle, 500 Hz frequency, but I want to generate 10%, 30%, 50%, 70% and 90% duty cycle. The clock frequency is 50 MHz. I want to generate a variable duty cycle from 5 variable frequency which are 500 Hz, 1 kHz, 50 kHz, 500 kHz, and 1 MHz. Please someone help me. I need your help. Thank you. DutyCycle(500Hz-10%).vhd DutyCycle500Hz_tb.vhd
  23. In this project, the instructor / educator in the target countries will use Basys 3 to teach digital systems. The object of the project. To change the theoretical type of learning in Ukraine, Georgia and Armenia to practice-oriented competence-based approach. To speed up integration between Higher Educational Institutes and business in target countries. To establish cooperation between EU and target countries in education and research. http://www.tempus-desire.eu/
  24. Tomar

    ARTY question

    Hi, I was wondering if it is right place to ask questions about Arty board. Thanks Tomar
  25. Takeways: 1. Maximize the usage of the Xilinx Zynq 7000 resources 2. Understand the nuances and internal workings of the Xilinx Zynq 7000 3. Trade-off performance vs. energy consumption Complexity of systems implemented using FPGA's are exponentially growing in a rapid pace. As a result of it most of the common design issues that a designer come across with ASIC SoC are becoming relevant with FPGA as well. If we consider Xilinx Zynq 7000 Programmable SoC, there is considerable processing power on the compute side. A simple migration is insufficient to achieve the same performance as discrete chips and also achieving performance and implementation benefits of such a complex FPGA would be very less. Estimating or identification of system performance and crucial bottlenecks much before writing RTL not just reduces the development time but also increases the Quality of Results. During this event we will be talking about how performance analysis and architecture exploration of a Zynq 7000 based System in the early stage of system development ensures that the right FPGA platform is selected and achieves optimal partitioning of the application onto the fabric. To Register, Click here