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Found 189 results

  1. Engr. Mubarak

    Vivado License Error of Export compliance

    Dear Sir, I am facing problem in getting license for Vivado Design Suite I have vouchers with written code on it found in FPGA kintex-7 box, but when we follow procedure by applying online it gives error of failure in export compliance verification I tried from different account and from different locations but error remained same. The Error is "We cannot fulfill your request as your account has failed export compliance verification. Please visit http://www.xilinx.com/support/answers/44043.html for a possible solution to resolve this error. "
  2. krusing

    Interfacing PMOD in Vivado

    I'm really new to this all, so apologies. I couldn't find a simple answer to my question about the PMOD connectors (specifically the standard PMOD JE) on the ZYBO. I have, for example, an 8 bit counter in VHDL. I want to output these 8 bits to JE. It's all very simple, but I'm not sure how to start. I've read tutorials which go far more complex than I want to right now. I've tried creating an IP block out of VHDL code, and I've also tried just adding the "Binary Counter" IP block. 1. How do I get a clock signal to input to the counter? I tried adding an IP called "Clocking Wizard," and running the Connection Automation. Then I get errors about being unable to place reset_rtl, which was an input created by the Connection Automation. 2. Is there a tutorial that I've missed somewhere, which outlines creating a simple design and outputting something on the PMOD pins?
  3. Mehdim

    AXI performance monitor

    Hello; have any of you guys had any experience with axi_perf_mon IP core? can you refer me to a help or tutorial of it?
  4. Hey there - total FPGA noob here. I just got my new Arty this week, and I've been looking at the tutorials on the Digilent site. I got at least one working (the basic "turn LCDs on and off with the switches" one) but would like to know how to build a simple project like that from scratch. I think it would be neat to maybe design an ALU or something, although that would require some input/output as well. Can anyone point me to a good way to a tutorial that would let me start a new project from scratch, instead of working from an existing base project? Thank you!
  5. Have anyone tried successfully to run the advanced I/O demo on nexys DDR ? https://reference.digilentinc.com/nexys4-ddr:userdemo I follow the instruction to create the project, when I run synthesis, it just cannot stop in the procedure.... I got three warnings. WARNING: [Vivado 12-4148] The synthesis checkpoint for IP 'C:/FPGA_project/Tutorial/Nexys4DDR-master/Projects/User_Demo/src/ip/PxlClkGen/PxlClkGen.xci' is not generated and IP is locked, no out-of-context (OOC) run will be created. The synthesis may not be able to complete or could result in incorrect behavior. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information. WARNING: [Vivado 12-4148] The synthesis checkpoint for IP 'C:/FPGA_project/Tutorial/Nexys4DDR-master/Projects/User_Demo/src/ip/ClkGen/ClkGen.xci' is not generated and IP is locked, no out-of-context (OOC) run will be created. The synthesis may not be able to complete or could result in incorrect behavior. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information. WARNING: [Runs 36-337] The following IPs are either missing output products or output products are not up-to-date for Implementation target. Since these IPs are locked, no update to the output products cant be done. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information. C:/FPGA_project/Tutorial/Nexys4DDR-master/Projects/User_Demo/src/ip/ddr/ddr.xci Run output log is uploaded. runme.log
  6. ColoradoAnalog

    Getting Started with Vivado guide

    I've seen several places in the information about the Arty board where it says I should read the "Getting Started with Vivado" guide. Where is this guide? I've searched for it and can not find it anywhere on the digilent website. Thank you.
  7. Mehdim

    how to define constraint

    Hello guys; Can anyone help me how to assign a port to specific pin in Vivado? I am using custom port on AX_GPIO module and I want to add it to one of PMOD connectors; I am using this command to connect it to V12 set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { gpio2_io_o }]; it works fine, but if I want to assign a vector port to some pins(for example gpio2_io_o[7:0] ) what should I do to define constraint?
  8. I've Verilog code generated from Matlab files using HDL Coder tool for Matlab. It is an adaptive filter design which requires speech signal input, that is to be sampled and given as inputs to my module. Do I need to install Vivado System Generator along with its corresponding Matlab configuration to implement a adaptive filter file on a Basys3 board? Or just install Vivado Design Suite and use XADC to sample the input signals, and implement it on board? Thanks, Shruthi Sampathkumar.
  9. gayathri90

    Bitstream And Zybo Board

    Hi.. I have been trying to use the GPIOs in Vivado 2014.1 Since, the Zybo board is not mentioned in the supported boards while creating the project, i have mentioned the package. I just want to read the switch value and print it in the console window in SDK. I had made the model, added the required constraints in the xdc file, generated the bitstream and then exported it to SDK. It worked fine. Next, i changed my design to read the status of the push button. Accordingly i changed the xdc file, generated the bitstream and exported to SDK. Now, after running the elf file, still the program is taking the values of switches and not the push buttons, I have tried cleaning up the project in SDK, resetting the runs in Vivado and generating the bitstream. But, still the values are read from switches. What would be the problem?? Can anyone help me at the earliest?? Thanks in advance
  10. Twoism

    Zybo base system design

    Hello, I've got some troubles while trying to fully understand the Zybo base system design. I need to replicate in my design (with Vivado 2015.4) the video part of the bsd, with the Axi display control ip. The design works but some points are not very clear to me: I've notice that 2 different clock sources are feed to the PL: (FCLK_CLK0 @ 100 MHz and FCLK_CLK1 @ 150 MHz). What is the reason behind this? Isn't 100 MHz enough for the VDMA? Why an Axi protocol converter is used? The design was build for an older version of Vivado (and ip library)? Thanks
  11. johnAbel

    What camera for Nexys video?

    I plan to use Nexys video for image processing. I did a project before where the FPGA gets the data straight from the sensor but now I will be using one of the interfaces (HDMI, USB, etc). There is a number of options, probably any of them valid, I'm just asking for suggestions. The most available cams have USB interface but Nexyx does not have 'pure' USBs unless I'm wrong and I'm not that much willing having an embedded processor just to interface USB to my video format stream. Second thing I though was to use the HDMI input but can't find many cameras with that output... Of course I want to avoid 'pro' and expensive cameras if I can get away with a £20 one. I've seen some USB to HDMI cables (I assume they have some chip somewhere), will they work? Has anybody used them for cameras, not for Pc to Screen? Third I also saw many WiFi cameras, so another option is to add some WiFi module to nexys and connect to the cam that way. As there will be a number of protocols in the middle, again, has anybody tried that before? Last I could just wire the CCD sensor to the I/O through the mezzanine connector, then I wonder why does it deserve to be called 'video' board. Any new suggestion also welcome, thanks guys! John
  12. JorgePascual

    Basys 3 Xilinx Vivado Design Suite Voucher

    Hi everyone! I'm Jorge an Electronics Engineer who want to buy the Basys 3 FPGA for the first time. I took some FPGA subjects at the University and I did some practical stuff using a Spartan 3 FPGA and Nexys 2 through ISE design suite. Now I want to have my own FPGA to continue learning myself and do some crazy stuff. Basys 3 description sais that it is not supported by xillinx ISE, so the only possibility is to use it through Vivado. My big doubt is: should I buy the 'Vivado Design Suite Voucher' together with the FPGA?? It is only 10$ difference. What is the difference between buy it or no? Can I generate the bytestream in Vivado without having the voucher? Finally, if I buy the 'Vivado Design Suite Voucher', when does the license finish? Should I buy 2 vouchers? Is it posible to use Vivado Voucher license in 2 pcs? my home pc and my laptop. Thanks for the help, I'm still quite new with this kind of programs and licenses. Up to now we used the ISE web pack. Regards
  13. Alex

    Intro Vivado Simulation

    Hi I have done an intro to vivado simulation in Verilog based on the assignment I have done in ISE http://m.instructables.com/id/How-to-Use-Vivado-Simluation/?ALLSTEPS
  14. PartyArty

    Nexys 4 DDR always is busy

    Just got a Nexys 4 DDR board for a class and the second I plugged it in, the busy light came on and it hasn't gone off yet and I get a message in Vivado when trying to connect it to the hw_server saying it may be locked by another hw_server?
  15. MrMcChicken

    Problem with installing board files

    Hello, I want to start using FPGAs. At this moment I have no board but I am hoping to get one soon. Yesterday I installed the Vivado WebPack edition 2015.4. Currently I want to learn how to use the Software. I have seen some Tutorials on the Digilent Wiki. So I wanted to install some board files to use with Vivado. Somehow I can not get them to be displayed on the 'Create New Project' wizard. I downloaded the board files and put the folders ( arty,nexys_video,nexys4 ... ) into: E:\Xilinx\Vivado\2015.4\data\boards\board_files. When I start a new project I enter a name at the first page. I skip the two 'Add/Remove Files' pages and then I try to select a board at the 'Solution Configuration' window. If I switch from 'Parts' to 'Boards' there are boards displayed but not those which are in the 'board_files' folder. The list contains eight Virtex boards. I have no Virtex board files in the 'board_files' folder. Is the location where I put the files wrong? I have already searched for other possible locations. It seems that the board which are listed are saved at: C:\Users\MrMcChicken\AppData\Local\Xilinx\DocNav\hubs\boards_and_kits If I chang the files there the list at the 'Create New Project' wizard doesn't changes. This confuses me just even more. How and where do I have to place the board files?
  16. Hi, I am implementing in Vivado the Arty's Microblaze based design that Adam Taylor posted on his website: http://adiuvoengineering.com/?p=626I I am having problems with it: Synthesis ran without any high importance warnings, but at the end of implementation I get three high severity warnings after I run the "Report Timing Summary": USB_UART_RXD: Port with no Input DelayUSB_UART_TXD: Port with no Input Delayddr3_sdram_reset_n: Port with no Output DelayI do not know how should I constrain these inputs and outputs. (Note: My Arty environment is working ok (board files have been downloaded and installed). I already have ran some basic logic circuits in the ARTY board successfully. My problems started with this project that includes the Microblaze and the uart) Attached are the snapshot of my block design (It is basically a copy of Adam Taylor's design) and a copy of the warnings I get. Let me know if I need to do something about these warnings, and if so, how, Thanks!
  17. Hi, Can Vivado Design Suite (installed on a single PC) support multiple device locked licences (using the voucher system) where development on more than one target board is desired?
  18. Hello, I just recently bought a zybo board and was following the digilent tutorial and almost finished the getting started project. However, I cannot make the helloworld.c file after launching the SDK. I can still program the PL side, but if I cannot utilize the PS side. SO now I basically have a standard FPGA until I can get this issue resolved. I have been looking through the xilinx forums too and haven't seen a good solution to this problem. here is an example of the console output and a screenshot of the error message that pops up Building file: ../src/helloworld.c Invoking: ARM gcc compiler arm-xilinx-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/helloworld.o" -I../../getting_started_with_ZYBO_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.d" -o "src/helloworld.o" "../src/helloworld.c" make: *** [src/helloworld.o] Error -1073741502
  19. One thing I learnt today was that Vivado has a Virtual I/O IP block, that allows you to see the state of signals deep in your design. You can also use it to inject signals into your design too. I've added a little project to my Wiki which connects the switches and LEDs on the Basys3 to an instance of the Virtual I/O block. http://hamsterworks.co.nz/mediawiki/index.php/Virtual_IO (Connecting to external I/O is not really the target end-use case - it would be perfect for monitoring status signals out of transceivers and memory controllers, or observing the state of misbehaving FSMs)
  20. WallyPhillips

    JTAG-SMT2

    I'm working with a VC709 development board that has a Digilent JTAG-SMT module on it. I installed Vivado 2015.4 Lab edition so I could program the VC709 with a .bit file. I plug the PC into the Digilent module via USB and the device managet says it doesn't recognize the USB device. When I try to "update driver", windows tells me it already has the latest driver installed. I tried installing Adept2 hoping the driver would be there but no luck. Adept doesn't see anything either. Is there a separate driver I need to install? Where do I get it? Thanks, Wally
  21. ntrstd11

    Modifying BRAM initial value quickly

    I'm using two inferred RAM modules which are assigned an initial state by reading lines from a file, as suggested to me previously here, in VHDL. The setup works fine, and all the RAM contents are loaded during synthesis properly. However, as my design is pretty large, it takes a lot of time to synthesize the project each time I need to only change the RAM initialization files. I need to synthesize very often while testing with different memory contents, my design being otherwise the same. Is there a way to only modify the memory contents of a design without having to synthesize the whole project? I tried using incremental builds but the improvement was not that effective.
  22. maton

    Configuring MIG for Arty board

    Hey there, I currently try to use the ddr memory on the arty board. Therefore you provide some files (I assume to configure the ddr within the MIG-7 IP) on your homepage. When I try to customize the MIG IP in my project (which is configured to the arty board, with the provided board files - Revision C - on your homepage), I try to load the provided .prj and .ucf file and the customization of the MIG-IP crashes. I googled the error and the xilinx homepage tells me the reason is that the artix-fpga on the arty board is not supported for MIG usage. Can anybody help me with this issue or maybe provide me an example project using the ddr on the arty board? EDIT: I use the vivado 15.2 design suite for development Best regards, Julian
  23. a2retro

    General Vivado question

    Until now I have always used the free ISE Webpack. One of the reasons i picked up the Arty was to finally try some of the advanced tools available in the design suite. While i understand the design suite is node and chip locked I was hoping I could dump my installs of ISE 13 and 14 and just use Vivado from now on, knowing the extra toolset would only work on the Artix 7 but all the other base tools should work ok?. Is this advisable or should i limit my use of Vivado to Artix7 only and keep using ISE 14 for all my other projects? Glenn
  24. I'm trying to initialize my design's block memory content, so that after the synthesis process and bitstream generation, the FPGA will boot up with some specific data in its memory cells. The BRAM I'm using is generated using the standard IP Block Memory Generator v8.2. The BRAM size I'm using is relatively large, about 128 Kbits, so my preference is to manually determine only the values of some portions of it. Is there a practical automated way to achieve all this in Vivado? Using Vivado, my initial approach was to use the "Load Init File" option in the IP generator dialog, and use a coe file. However, this did not seem to have any effect once I programmed my Basys 3 board, I'm suspecting that coe files for initialization are not synthesizable. Is this true?
  25. Hello, I'm developing a bare metal application in Zybo for a subject this semester and I want to run two tasks in parallel taking advantage of the dual processor in the Zynq. I want to know how can I use the dual core capabilities of the Cortex A9 processor in the Zybo in a bare metal application, configuring it from Vivado. I found this tutorial in Xilinx documentation but it uses the EDK instead of Vivado. If you can lead me to more resources where I can learn how to do this I'll be really thankful. Thank you very much.