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Found 182 results

  1. gayathri90

    Bitstream And Zybo Board

    Hi.. I have been trying to use the GPIOs in Vivado 2014.1 Since, the Zybo board is not mentioned in the supported boards while creating the project, i have mentioned the package. I just want to read the switch value and print it in the console window in SDK. I had made the model, added the required constraints in the xdc file, generated the bitstream and then exported it to SDK. It worked fine. Next, i changed my design to read the status of the push button. Accordingly i changed the xdc file, generated the bitstream and exported to SDK. Now, after running the elf file, still the program is taking the values of switches and not the push buttons, I have tried cleaning up the project in SDK, resetting the runs in Vivado and generating the bitstream. But, still the values are read from switches. What would be the problem?? Can anyone help me at the earliest?? Thanks in advance
  2. Twoism

    Zybo base system design

    Hello, I've got some troubles while trying to fully understand the Zybo base system design. I need to replicate in my design (with Vivado 2015.4) the video part of the bsd, with the Axi display control ip. The design works but some points are not very clear to me: I've notice that 2 different clock sources are feed to the PL: (FCLK_CLK0 @ 100 MHz and FCLK_CLK1 @ 150 MHz). What is the reason behind this? Isn't 100 MHz enough for the VDMA? Why an Axi protocol converter is used? The design was build for an older version of Vivado (and ip library)? Thanks
  3. johnAbel

    What camera for Nexys video?

    I plan to use Nexys video for image processing. I did a project before where the FPGA gets the data straight from the sensor but now I will be using one of the interfaces (HDMI, USB, etc). There is a number of options, probably any of them valid, I'm just asking for suggestions. The most available cams have USB interface but Nexyx does not have 'pure' USBs unless I'm wrong and I'm not that much willing having an embedded processor just to interface USB to my video format stream. Second thing I though was to use the HDMI input but can't find many cameras with that output... Of course I want to avoid 'pro' and expensive cameras if I can get away with a £20 one. I've seen some USB to HDMI cables (I assume they have some chip somewhere), will they work? Has anybody used them for cameras, not for Pc to Screen? Third I also saw many WiFi cameras, so another option is to add some WiFi module to nexys and connect to the cam that way. As there will be a number of protocols in the middle, again, has anybody tried that before? Last I could just wire the CCD sensor to the I/O through the mezzanine connector, then I wonder why does it deserve to be called 'video' board. Any new suggestion also welcome, thanks guys! John
  4. JorgePascual

    Basys 3 Xilinx Vivado Design Suite Voucher

    Hi everyone! I'm Jorge an Electronics Engineer who want to buy the Basys 3 FPGA for the first time. I took some FPGA subjects at the University and I did some practical stuff using a Spartan 3 FPGA and Nexys 2 through ISE design suite. Now I want to have my own FPGA to continue learning myself and do some crazy stuff. Basys 3 description sais that it is not supported by xillinx ISE, so the only possibility is to use it through Vivado. My big doubt is: should I buy the 'Vivado Design Suite Voucher' together with the FPGA?? It is only 10$ difference. What is the difference between buy it or no? Can I generate the bytestream in Vivado without having the voucher? Finally, if I buy the 'Vivado Design Suite Voucher', when does the license finish? Should I buy 2 vouchers? Is it posible to use Vivado Voucher license in 2 pcs? my home pc and my laptop. Thanks for the help, I'm still quite new with this kind of programs and licenses. Up to now we used the ISE web pack. Regards
  5. Alex

    Intro Vivado Simulation

    Hi I have done an intro to vivado simulation in Verilog based on the assignment I have done in ISE http://m.instructables.com/id/How-to-Use-Vivado-Simluation/?ALLSTEPS
  6. PartyArty

    Nexys 4 DDR always is busy

    Just got a Nexys 4 DDR board for a class and the second I plugged it in, the busy light came on and it hasn't gone off yet and I get a message in Vivado when trying to connect it to the hw_server saying it may be locked by another hw_server?
  7. MrMcChicken

    Problem with installing board files

    Hello, I want to start using FPGAs. At this moment I have no board but I am hoping to get one soon. Yesterday I installed the Vivado WebPack edition 2015.4. Currently I want to learn how to use the Software. I have seen some Tutorials on the Digilent Wiki. So I wanted to install some board files to use with Vivado. Somehow I can not get them to be displayed on the 'Create New Project' wizard. I downloaded the board files and put the folders ( arty,nexys_video,nexys4 ... ) into: E:\Xilinx\Vivado\2015.4\data\boards\board_files. When I start a new project I enter a name at the first page. I skip the two 'Add/Remove Files' pages and then I try to select a board at the 'Solution Configuration' window. If I switch from 'Parts' to 'Boards' there are boards displayed but not those which are in the 'board_files' folder. The list contains eight Virtex boards. I have no Virtex board files in the 'board_files' folder. Is the location where I put the files wrong? I have already searched for other possible locations. It seems that the board which are listed are saved at: C:\Users\MrMcChicken\AppData\Local\Xilinx\DocNav\hubs\boards_and_kits If I chang the files there the list at the 'Create New Project' wizard doesn't changes. This confuses me just even more. How and where do I have to place the board files?
  8. Hi, I am implementing in Vivado the Arty's Microblaze based design that Adam Taylor posted on his website: http://adiuvoengineering.com/?p=626I I am having problems with it: Synthesis ran without any high importance warnings, but at the end of implementation I get three high severity warnings after I run the "Report Timing Summary": USB_UART_RXD: Port with no Input DelayUSB_UART_TXD: Port with no Input Delayddr3_sdram_reset_n: Port with no Output DelayI do not know how should I constrain these inputs and outputs. (Note: My Arty environment is working ok (board files have been downloaded and installed). I already have ran some basic logic circuits in the ARTY board successfully. My problems started with this project that includes the Microblaze and the uart) Attached are the snapshot of my block design (It is basically a copy of Adam Taylor's design) and a copy of the warnings I get. Let me know if I need to do something about these warnings, and if so, how, Thanks!
  9. Hi, Can Vivado Design Suite (installed on a single PC) support multiple device locked licences (using the voucher system) where development on more than one target board is desired?
  10. Hello, I just recently bought a zybo board and was following the digilent tutorial and almost finished the getting started project. However, I cannot make the helloworld.c file after launching the SDK. I can still program the PL side, but if I cannot utilize the PS side. SO now I basically have a standard FPGA until I can get this issue resolved. I have been looking through the xilinx forums too and haven't seen a good solution to this problem. here is an example of the console output and a screenshot of the error message that pops up Building file: ../src/helloworld.c Invoking: ARM gcc compiler arm-xilinx-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/helloworld.o" -I../../getting_started_with_ZYBO_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.d" -o "src/helloworld.o" "../src/helloworld.c" make: *** [src/helloworld.o] Error -1073741502
  11. One thing I learnt today was that Vivado has a Virtual I/O IP block, that allows you to see the state of signals deep in your design. You can also use it to inject signals into your design too. I've added a little project to my Wiki which connects the switches and LEDs on the Basys3 to an instance of the Virtual I/O block. http://hamsterworks.co.nz/mediawiki/index.php/Virtual_IO (Connecting to external I/O is not really the target end-use case - it would be perfect for monitoring status signals out of transceivers and memory controllers, or observing the state of misbehaving FSMs)
  12. WallyPhillips

    JTAG-SMT2

    I'm working with a VC709 development board that has a Digilent JTAG-SMT module on it. I installed Vivado 2015.4 Lab edition so I could program the VC709 with a .bit file. I plug the PC into the Digilent module via USB and the device managet says it doesn't recognize the USB device. When I try to "update driver", windows tells me it already has the latest driver installed. I tried installing Adept2 hoping the driver would be there but no luck. Adept doesn't see anything either. Is there a separate driver I need to install? Where do I get it? Thanks, Wally
  13. Hi, I'm not able to fully understand the relation between the Board file and the Constraints file in Vivado. In my design I need to connect a custom IP block to a Pmod connector on a ZYBO board. I've loaded the XML board file provided by Digilent but now I'm not anymore able to customize the pins as i would do with a constraint file since it seem to me that the mapping it is now specified in the XML file. # Pmod connector JB set_property PACKAGE_PIN T20 [get_ports {d_out[0]}] set_property PACKAGE_PIN U20 [get_ports {d_out[1]}] set_property PACKAGE_PIN V20 [get_ports {d_out[2]}] set_property PACKAGE_PIN W20 [get_ports {d_out[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {d_out[*]}]Should I need to add a constraint file even if the Board port mapping is already specified by the board file? Is this a good practice? Thanks
  14. ntrstd11

    Modifying BRAM initial value quickly

    I'm using two inferred RAM modules which are assigned an initial state by reading lines from a file, as suggested to me previously here, in VHDL. The setup works fine, and all the RAM contents are loaded during synthesis properly. However, as my design is pretty large, it takes a lot of time to synthesize the project each time I need to only change the RAM initialization files. I need to synthesize very often while testing with different memory contents, my design being otherwise the same. Is there a way to only modify the memory contents of a design without having to synthesize the whole project? I tried using incremental builds but the improvement was not that effective.
  15. maton

    Configuring MIG for Arty board

    Hey there, I currently try to use the ddr memory on the arty board. Therefore you provide some files (I assume to configure the ddr within the MIG-7 IP) on your homepage. When I try to customize the MIG IP in my project (which is configured to the arty board, with the provided board files - Revision C - on your homepage), I try to load the provided .prj and .ucf file and the customization of the MIG-IP crashes. I googled the error and the xilinx homepage tells me the reason is that the artix-fpga on the arty board is not supported for MIG usage. Can anybody help me with this issue or maybe provide me an example project using the ddr on the arty board? EDIT: I use the vivado 15.2 design suite for development Best regards, Julian
  16. a2retro

    General Vivado question

    Until now I have always used the free ISE Webpack. One of the reasons i picked up the Arty was to finally try some of the advanced tools available in the design suite. While i understand the design suite is node and chip locked I was hoping I could dump my installs of ISE 13 and 14 and just use Vivado from now on, knowing the extra toolset would only work on the Artix 7 but all the other base tools should work ok?. Is this advisable or should i limit my use of Vivado to Artix7 only and keep using ISE 14 for all my other projects? Glenn
  17. I'm trying to initialize my design's block memory content, so that after the synthesis process and bitstream generation, the FPGA will boot up with some specific data in its memory cells. The BRAM I'm using is generated using the standard IP Block Memory Generator v8.2. The BRAM size I'm using is relatively large, about 128 Kbits, so my preference is to manually determine only the values of some portions of it. Is there a practical automated way to achieve all this in Vivado? Using Vivado, my initial approach was to use the "Load Init File" option in the IP generator dialog, and use a coe file. However, this did not seem to have any effect once I programmed my Basys 3 board, I'm suspecting that coe files for initialization are not synthesizable. Is this true?
  18. Hello, I'm developing a bare metal application in Zybo for a subject this semester and I want to run two tasks in parallel taking advantage of the dual processor in the Zynq. I want to know how can I use the dual core capabilities of the Cortex A9 processor in the Zybo in a bare metal application, configuring it from Vivado. I found this tutorial in Xilinx documentation but it uses the EDK instead of Vivado. If you can lead me to more resources where I can learn how to do this I'll be really thankful. Thank you very much.
  19. I've successfully installed Vivado 2015.3 webpack and generated a bitstream for the Arty GPIO demo. On Linux, the Xilinx installer does not install "cable drivers"; apparently you are supposed to install those yourself, somehow. But I am sure not what I need for the built-in JTAG on the Arty board. Do I want Adept 2 Runtime or something else? From within the Vivado HW Manager I don't see any driver-install options, and it presently says it cannot find any hardware attached. Thanks.
  20. mavinjit

    Hello! New FPGA user!

    Hello everyone. My name is Mavin and I am currently in my final year of my undergraduate program. For my Final Year Project, I have been tasked to use an FPGA for Image Tracking and Surveillance. (Basically my program must be able to detect a certain coloured image and 'lock' onto it wherever it moves) I am really new to FPGAs (just got the ARTIX 7 Nexys 4 FPGA), and my professor has told me to work on a simple program - (when a switch is turned on, numbers from 1-10 will be shown on the 7 - segment LED display) I have learnt C++ before and used Microsoft Visual Studios in my earlier days. But i am completely new to this software - Vivado. Could anyone point me in the right direction? Thank you!
  21. DigilentStudio

    Basys 3 - binary output pin for temperature sensor

    Muthupriya Somasundaram posted this question on the Getting started with Vivado and Basys3 video: Hi, I registered in the digilentic forum, but i couldn't able to post any question. I am using a temperature sensor to measure the environment temperature and connected the sensor output to XADC. Now,form which pin do i need to get the binary output and the output will be in how many bits? Thanks in advance! Regards, Priya
  22. Commanderfranz

    Vivado and Windows 10 Fix

    A lot of people haven't been able to upgrade to Windows 10 because Vivado will stop working.
  23. Tunai Porto

    Vivado Issue (License)

    Greetings Digilent Staff, I recently bought a Basys 3 to use in a VLSI Desgin course of my university (Cal State Long Beach). I did all the steps on the video tutorial you guys posted on youtube to upload my first project to the board. However, in the "synthesis" part, I keep getting this error, even though I already acquireda license: "[Common 17-345] A valid license was not found for feature 'Synthesis' and/or device 'xc7a35t'. Please run the Vivado License Manager for assistance in determiningwhich features and devices are licensed for your system."What should I do? Since I am only doing simple projects, I did not think it would be necessary to buy the$10 key for the Vivado software. Should I do that? What can I do now? Thank you very much for your attention.
  24. digicloud14

    Importing EDK Pcore into Vivado?

    Hi all, I found a project from GoPro for the Zybo Zynq 7000 development board (link to project) that makes use of the HDMI port on the board as an hdmi receiver. The project is in EDK and not Vivado however. For a personal project I am trying to accomplish, I would like to make use of the HDMI rx since the base system design only includes a hdmi tx by default. Is it possible to take the hdmi_rx pcore files and import them into vivado somehow so that I may create an HDMI rx block in the ip integrator? If anyone could point me towards a guide or tutorial for this, I would be extremely grateful. Thanks, Chris
  25. When asking the question below to sales department I was reffered to this forum. I would like to know if I can install this Basys3-locked version of Vivado Design Edition on several computers since it's bound to the Basys3 hardware ? So I can use the board on different PCs. Or is it only valid for one PC at a time ? If so can this version be moved from one PC to another ?