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Found 147 results

  1. Hello everyone, I use 1 pin of the pmod connector of the basys3 board for receiving a signal. So in the .xdc file i set every right but I need to say that the incoming signal is not a clock. In the help it suggests "set_property CLOCK_DEDICATED_ROUTE value [get_nets net_name]". I changed the net_name with the signal name "set_property CLOCK_DEDICATED_ROUTE value [get_nets echo_pin]" but u get this critical warning "Invalid option 'FALSEecho_pin' specified for'objects'. anyone an idee? thank you
  2. Hi, I am trying to learn verilog and digital design using basys3 and vivado (webpack) tools. I implemented a jk flip flop using the following logic: module jk_flip_flop ( input [1:0] sw, input clk, input btnC, output reg [0:0] led); always @ (posedge clk) begin if (btnC == 1) led[0] = 0; else begin if (sw[0] == 1) begin if (sw[1] == 1) led[0] <= ~led[0]; else led[0] <= 1; end else begin if (sw[1]) led[0] <= 0; end end end endmodule What I see is when sw[0] and sw[1] are both 1 and if the previous led state was 1, the led does not turn off completely (it just gets dimmer). What could be the problem here, and how would I go about fixing it? I also tried using other LEDs on the board and each had the same problem. Thanks.
  3. Arty-Z7-20 board

    Hello, i have since a few days a new arty-z-20 board and i like to learn from the rare examples for that board. I found one example which seems to be the base for Linux (Arty-Z7-20-linux_bd-master). This example was made with the Vivado 2016.4 Suite, but i use the current Vivado Suite (2017.3). In that example are two ip`s that could not be upgraded, because they no longer exists in the current Vivado Suite. Where can i get some working examples with Vivado 2017.3 and higher Support for my new Arty-Z7-20 board? My first Arty board was the Artix-7 "original" board. I had found all the examples that i needed to learn from the beginning to the full scale microblaze architecture. I made good experiences, but now i'am not happy with that arty-Z7-20 board! How do i build the simplest Zynq architecture with UART and "bare metal" OS? How do i build the very easiest Linux architecture and what ip's do i need for that? I have a lot more questions... Thank you...
  4. Creating a 25 Mhz clock on the Basys 3

    Hello Forum , Its my first Post so I hope it helps everyone I have this code for generating a 25 Mhz clock having a 50 Mhz clock as main using the basys3 board. I use the LSB as the clock because it will goes 1/2 of the main clock of 50Mhz *//////////////////////* START OF CODE //Clock module clkdiv( input wire mclk , input wire clr , output wire clk25 ); reg [24:0] q; always @(posedge mclk or posedge clr) begin if(clr == 1) q <= 0; else q <= q+1; end assign clk25 = q[0]; endmodule *////////////////////////* END OF CODE So whenever I want to call it I just make a instance of this class. In Vivado, when I open my synthesized project and click [Tools ---> Edit devices properties] This is where I select my clock frequency as 50 MHZ { Please see image attached } So my questions are : Is this the proper way to set up a clock using Vivado and the Basys3 Board?In the main page of the Basys3 it says that one can get a clock as high as 450 Mhz but in the options of the [Tools ---> Edit devices properties] I can only find clocks as high as 66 MhzAnd just some basic ones Why Vivado takes sooo long to synthesized, implement and generate the bitstream of an easy and small code? Just implementing in hardware an AND gate takes me 5 minnutes to download the program to the board. Is there a quicker way ? Thanks Forum .
  5. Hello, I have a Nexys 4 DDR board and I was going through the tutorial. I installed the suite and when I reach the point to connect the target, Vivado is unable to find it. The jumper of the JTAG is right and I tried more than one USB cable. The error I get on Vivado is "No hardware targets exist on the server [TCP:localhost:3121]" Your help is appreciated. Ahmed
  6. are there any tutorials for dummies on getting a zybo board to produce a tone? one that thoroughly explains its steps?
  7. Arty hello world

    Hello to all, I'm a college student with a bit of arduino experience. I got ARTY because I have a course that requires learning the VHDL rudiments. (the choice of board was free, I hope I made a good choice!) My goal would be to start with a very simple project, maybe turn on some LEDs by pushing the buttons and getting familiar with the development environment. I am currently using Vivado 2017 and I have managed to have arty in the project board list. After that I do not know what to do, and I did not find a giuide for dummies that explained how to get to my goal. I have to use VHDL and for now my goal is to have a code as clean as possible and essential (also at the expense of not using all the potential of the board) I hope it is a not too complex and accessible request happy to start
  8. This issue had been a pain ever since I started using the CMDO-A7 devices. In Windows 7, using Vivado 2016.2, if I open the hardware manager in Vivado to configure the device, after a few minutes Vivado decides that the target is no longer available and disconnects it. This is a particular problem when I am also using the USB UART... though the problem doesn't happen immediately. This issue makes using the ILA extremely difficult to impossible with this board. When I use the Adept Utility for Windows to configure the board I can use the UART all day without a problem. I suspect a JTAG/UART driver related issue is to blame.
  9. Greetings, I am currently working on a Digilent Zybo Trainer Board with a Zynq 7010 chip. Everything works fine from hardware up to software running on the board as long as it is launched directly from the Xilinx SDK. However, the software hangs up indefinitely whenever the Xil_In32() function is called ONLY when booting from non-volatile memory (QSPI flash or SD card). I have followed the prescribed process of making an FSBL, creating a boot image (with (bootloader)FSBL.elf, hw_wrapper.bit, main_project.elf) and programming the BOOT.bin file to flash memory successfully. The FSBL calls the 'ps7_init()' and ps7_post_config()' functions. My research shows that this issue revolves around enabling the level shifters, but as far as I can tell this occurs in the ps7_post_config() function. Any help would be appreciated. Details: Hardware: Zybo Trainer Board (Zynq 7010) Hardware peripherals: XADC Wizard, AXI GPIO Project: standalone C project Vivado 2017.2 Xilinx SDK 2017.2 OS: Windows 7 Enterprise SP1
  10. BASYS3 with Microblaze in Vivado 16.x

    I have been trying to implement a simple Hello World program using a Microblaze IP on a BASYS3 board using Vivado 16.1 and 16.2. I have had success using the Microblaze MCS design shown in figure mb1.pgn below, which shows that the board and interface works. However, after many attempts I have never been able to get the design working using a Microblaze, as shown in image mb2. png below. My simple question is, has anyone gotten the Microblaze to work on a BASYS3 using the free Web version of Vivado 16.1 or 16.2? Here is some additional information, for anyone interested: To get the Microblaze MCS design to work, it’s important that "reset" is set to Active High. Also, when creating the ELF file I use the following approach which seems to work fine in Vivado 16.x: Create the complete block design and the design wrapper; run synthesis and then File / Export the Hardware (without including the bitstream;) then File / Launch SDK. In SDK, use File / New Application Project and select the Hello World application. After SDK creates (automatically) the ELF file, associate it in Vivado with the design under Tools \ Associate ELF file; finally, in Vivado generate the bitstream and then in the Hardware Manager program the BASYS3 board and observe the UART output with a terminal program. As I said, this seems to work without any problems with the Microblaze MCS but not the Microblaze. Strangely, the Microblaze design does not create any error messages or obvious warnings. Greatly appreciate any insight. Thanks.
  11. PikeOS project on ZC702

    Greetings all, I'm facing some issues in running my PikeOS project on zc702 board Following are some brief steps that i took to make PikeOS's project i selected a pikeOS integrated project, using devel-apex demo template Board Parameters Description: Xilinx Zynq-7000 All Programmable SoC ZC702 Evaluation kit. Architecture: arm Processor: v7hf Boot Strategy: uboot_dtb then in project Configuration, set path of binery to run on partition. on boot, it generate a file name, apex-devel-zynq-zc702-uboot in order to boot this project on board using sd card few more files are required. This is where i'm lost, can't figure how to generate those files, or where to find then. Hopefully Someone can help me. Thank You.
  12. Nexys Video No Hardware Target Exists

    I am trying to operate the Nexys Video development board using the vivado hardware manager on a windows 8 system. However I keep getting No hardware targets exist on the server error. Steps i have taken to remedy the situation include: Re-installed Vivado with included cable drivers Tried different versions of vivado Tried on a different PC Formatted PC and installed vivado Updated FTDI drivers Tried 3 different (new) USB cables Installed cable drivers manually The programming jumper is in the right position (jtag), the USB cable is plugged into the correct (prog) port and the board is powered. Can anyone suggest anything else I might try to fix the issue? Thanks.
  13. NEXYS4 board cannot be detected

    Hi, I just installed vivado 2017.2 on my PC, running windows 7 Service Pack1 (64-bit). I connected my Nexys 4 board using the cable that comes with the board in the package. When I attempted to connect the board to my PC, by clicking Open Hardware Manager -> Open Target -> Auto Connect, in the Hardware window in vivado, it shows localhost(0), which means no device detected. I also get 2 warnings below: warning: cannot open library dpcomm.dll, first required symbol ftdimgr_lock, Digilent FTDI based JTAG cables cannot be supported warning: cannot open library djtg.dll, first required symbol DjtgGetPortCount, select Digilent JTAG cables cannot be supported I noticed a post in a non-English Digilent forum, in which someone else was experiencing the exact same issue. Please help. yy
  14. Best Vivado license option on Zedboards

    Hello I want to buy a Zedboard to evaluate to possibly replacing our existing embedded computer solution (Kontron ETX computer module on a baseboard) with a ZYNQ 7000 based solution. I work at a research institute with a very strong mandate to train students. We will probably put a student on this job to investigate, so we might be able to qualify for the Academic edition of the Zedboard. My question is related to the licenses (vouchers) that come bundled with the zedboards by the various resellers. 1. On the zedboard.org site http://zedboard.org/sites/default/files/product_briefs/PB-AES-Z7EV-7Z020_G-v12.pdf they state: A. (AES-Z7EV-7Z020-G) ZedBoard Commercial Edition (Available Exclusively from Avnet) I have contacted local Avnet rep which stated that this board comes with the Vivado HL Design edition node lock licence valid for 1 year. B. (ZEDBOARD) ZedBoard Academic Edition (Available Exclusively from Digilent) I have contacted digilent which indicate that this board comes with a node locked SDSoC licence valid for 1 year. 2. Looking at other suppliers like Digikey and Mouser (http://www.digikey.com/products/en?keywords=ZEDBOARD) you find -when searching the datasheet- that they provide a voucher for Chipscope licence only. You use webpack with these boards. Now I know that Vivado Webpack should be enough but I want to maximize value by purchasing the most valuable license for our particular application. I would want the student to have maximum flexibility. I think elements that are important are. 1. Good simulation and debugging capabilities i.e. embedded logic analyser, chipscope and a version of ISIM with more features than that shipped with webpack. 2. Good tools for C/C++ software development. We would be looking at integrating EPICS in our solutions. 3. Also access to more IP cores not available in Webpack would also be interesting to evaluate. We would be looking at integrating EtherCAT into our solutions. 4. It would also be nice to do High Level synthesis work (HLS) using C. Please advise me on which resellers' product supply the best/most valuable licensing option. Thank you Chris
  15. I have successfully used Vivado to store the bitstream into flash. On power-up, however, it does not program itself. If I push the PROG button, it does load the program from flash. That takes about 6 seconds. Two questions: 1. how do I get the program to auto-load? 2. how can I get it to load faster? the default program from Digilent loads in under a second. Thanks!
  16. Zybo webserver

    Dear, At the moment me and and a few friends are testing different IOT's. To upload data from a microcontroller or fpga to a webserver. Or upload to our website with $ comments. So our website will place the value's in the webserver. Now our question is. How can we connect our zybo board to the internet. We know we need to use the ethernet port but its very hard to find any information about uploading data with the zybo board. We use the zybo board with the vivado 2016 version. Greetings, Niels
  17. Arty Z7 HDMI IN issue

    Hello Guys, I just received my Arty Z7 board and I was trying out the HDMI_IN design. I exactly followed the given instructions and I get this place_design error in vivado and "The Hardware Project referenced by this BSP (hdmi_in_bsp) was not found in this workspace." in sdk. I tried out the HDMI_OUT and it was working perfectly fine. I have attached the screenshots. Kindly help me out here. Note: I have seen similar questions on this forum, but none of those solutions helped me. So starting a new thread. TIA Regards, Karthik
  18. I'm attempting the GPIO demo with a new Arty Dev board and running into the following error. I'm following instructions here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start Which is good until step #4. And if I uncheck "include bitstream", I get this error on the console: "Cannot write hardware definition file as there are no IPI block design hardware handoff files present" Since I'm new to Vivado development, this puts me at a dead stop. Thanks!
  19. Hi, I am running through the Creating a Custom IP core using the IP Integrator tutorial using Vivado 2017.2 and have run into a number of problems as follows. In section 4.1) Adding the the line, parameter integer PWM_COUNTER_MAX = 1024, Causes Vivado to mark the line with the warning, Warning: syntax error near "Integer". In section 4.2) Adding the lines, output wire PWM0, output wire PWM1, output wire PWM2, output wire PWM3, Causes Vivado to mark the first line with the warning, Warning: syntax error near "wire". In section 4.3) Adding the line, reg [15:0] counter = 0; Causes Vivado to mark the first line with the warning, Warning: syntax error near "15". Adding the remainder of this section causes a number of errors reporting that has not been declared. I have attached the VHDL file that I am working on. Any ideas why I am getting these issues? Forgive me as my VHDL is not very good at the moment and the issues I am having are probably only minor. Regards FarmerJo my_pwm_core_v1_0_S00_AXI.vhd
  20. Nexys4 DDR: Fix hold time violation

    Hi, I am using Vivado 2016.4 to program the Nexys4 DDR 7-segment display. I have a very simple VHDL project, which works as follows: 100 MHz clock is used to increment an 8-bit counter when this counter overflows, it inverts the value of a local signal called "slowclk". Hence, "slowclk" is "clk" divided by 512. the "slowclk" is used to increment another 8-bit counter, the output of which is assigned to the 7-segment display segment selector pins on the board. Complete VHDL source: Note: I understand that given such division, the effect on the digit segments will still not be visible - I just want to demonstrate the timing problem. However, the design fails to meet timing constraints as follows in attached pictures: Timing constraint failures in more detail, including the full source VHDL: Clock routing on the FPGA: The following is the .xdc constraints file (commented-out definitions are omitted): From what little I know about FPGA clock routing and resources, I understand this to be due to the high-frequency clock and associated logic being in different regions to each other, thus requiring the implementation run to route the clock signal through awkward paths; as a consequence, the total signal propagation time is such, that before the logic relevant to the current clock pulse is evaluated, the next clock front is already present. Am I correct in this thinking? And in either case, how can I fix the timing issues that Vivado warns about?
  21. Using Zybo Audio Codec W/base Design

    Hi all, I'm trying to get something working with the audio codec on the Zybo board. In the end, I want to sample an electronic musical instrument, do some signal processing, and output the processed signal, but for now I'm trying to get the demo from the base design working. I can get the demo to work using the supplied bit stream by creating an SDK project with the bitstream provided in the project files. If I open the PL project in a newer version of Vivado (2014.3), upgrade the IP cores, generate a bitstream, and run the demo from the SDK as before, the program hangs and doesn't print anything to the terminal. I've narrowed down where the program hangs using print statements to when the audio codec is being initialized. In particular, it seems that the code has an issue with the "Xil_Out32()" around line number 146 of the audio_demo.c file. To me this likely means that there is an issue with the programmable logic, so perhaps when I upgraded the IP cores for the new version of VIvado? I've also tried deleting the generic IP cores in the block design and running the connection automation, but with the same results. I am using an external supply to power the board with 5V and a max of 1A, so that shouldn't be an issue. I'm curious if anybody else has tackled something like this and/or updated the Zybo base design for newer versions of Vivado. -J
  22. How to add own logic to Arty board flow?

    The Arty board examples and tutorials use the Vidado drag and drop editor. But, there is no example how one would add their own custom logic. I have hacked this so far by dropping a peripheral and then replacing the stub verilog file, but it would help to show how this should be done. The natural would be to drop in a custom bus i/f file (e.g. using the AXI to AHB or AXI to APB bridge to a stub) and also how you add pins to the port list. Hacking away at it seems just wrong - if there is some intended flow, it is not apparent. The old way of editing the .ucf file and adding the ports to the top file does not seem like a fit for this SDK/Microblaze environment. Thanks, Paul
  23. Zybo XADC Demo

    Hello, I'm trying to run the file "XADC demo for ZYBO" with the tutorial "Using Digilent Github Demo Projects". First i downloaded the ZIP file "Zybo-XADC-2016.4-1" from "Github". I didn't select the “SDK Hardware Handoff” option because the project dose not supports Vivado SDK so i select the “Vivado” option. I did all the steps and when i get to step 3 "Generate Bitstream" ,I click Generate Bitstream on the left hand menu towards the bottom and click OK the "synthesis and implementation" are failed because 3 errors. i'm adding a print screen of the errors. Has anyone encountered this problem? Is there a problem with the file itself? Is there a problem with the C code? Thank you for any help!
  24. Hi - I just tried to install the XUP USB-JTAG Programming Cable from diligent. I also have a Diligent Programming Cable. Centos can see both cables (see below) Vivado can see the Diligent programming cable but not the Xilinx one. Given the physical constraints of the installation only the Xilinx one will work. Are there any specific instructions to get the Xilinx cable going? $lsusb | grep "Xilinx/|Future" Bus 002 Device 003: ID 03fd:000d Xilinx, Inc. Bus 001 Device 006: ID 0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC
  25. Centos Vivado Xilinx JTAG Cable

    Hi - I just tried to install the XUP USB-JTAG Programming Cable from diligent. I also have a Diligent Programming Cable. Centos can see both cables (see below) Vivado can see the Diligent programming cable but not the Xilinx one. Given the physical constraints of the installation only the Xilinx one will work. Are there any specific instructions to get the Xilinx cable going? $lsusb | grep "Xilinx/|Future" Bus 002 Device 003: ID 03fd:000d Xilinx, Inc. Bus 001 Device 006: ID 0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC