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Found 189 results

  1. Hi, I'm not able to fully understand the relation between the Board file and the Constraints file in Vivado. In my design I need to connect a custom IP block to a Pmod connector on a ZYBO board. I've loaded the XML board file provided by Digilent but now I'm not anymore able to customize the pins as i would do with a constraint file since it seem to me that the mapping it is now specified in the XML file. # Pmod connector JB set_property PACKAGE_PIN T20 [get_ports {d_out[0]}] set_property PACKAGE_PIN U20 [get_ports {d_out[1]}] set_property PACKAGE_PIN V20 [get_ports {d_out[2]}] set_property PACKAGE_PIN W20 [get_ports {d_out[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {d_out[*]}]Should I need to add a constraint file even if the Board port mapping is already specified by the board file? Is this a good practice? Thanks
  2. A recent change to the demonstration Cmod-A7-35 GPIO example (and others) here https://github.com/Digilent/Cmod-A7-35T-GPIO/commit/7bc1448626433ee2c2f493e48bf7b69a76b208b2#diff-a1605eb6dd43eccff08627ccfcfd10fd has removed the create_project.tcl file, which is referenced in your documentation here https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start Can you please point me to updated "how to get started" documentation that is valid for vivado 2018.2 and the latest source code repository changes? Thank you
  3. This issue had been a pain ever since I started using the CMDO-A7 devices. In Windows 7, using Vivado 2016.2, if I open the hardware manager in Vivado to configure the device, after a few minutes Vivado decides that the target is no longer available and disconnects it. This is a particular problem when I am also using the USB UART... though the problem doesn't happen immediately. This issue makes using the ILA extremely difficult to impossible with this board. When I use the Adept Utility for Windows to configure the board I can use the UART all day without a problem. I suspect a JTAG/UART driver related issue is to blame.
  4. Hi All, Is there anybody have any experience about XUP (Xilinx University Program) USB-JTAG Programmer Revision-G using with Vivado 2015 or 2018? I have some little experience with Vivado 2015.5 and 2018.1 but regarding my experiences XUP USB-JTAG Programmer is not compatible with Vivado? I tried all ways on Centos-7 OS and the particular script (install_drivers.tar.gz). I aimed to program the Zedboard for petalinux applications developing but no success with XUP USB-JTAG Rev.G and Vivado running on Centos-7. Could you please share any suggestions if you have? Regards. Kursat Gol
  5. abcdef

    BASYS3 with Microblaze in Vivado 16.x

    I have been trying to implement a simple Hello World program using a Microblaze IP on a BASYS3 board using Vivado 16.1 and 16.2. I have had success using the Microblaze MCS design shown in figure mb1.pgn below, which shows that the board and interface works. However, after many attempts I have never been able to get the design working using a Microblaze, as shown in image mb2. png below. My simple question is, has anyone gotten the Microblaze to work on a BASYS3 using the free Web version of Vivado 16.1 or 16.2? Here is some additional information, for anyone interested: To get the Microblaze MCS design to work, it’s important that "reset" is set to Active High. Also, when creating the ELF file I use the following approach which seems to work fine in Vivado 16.x: Create the complete block design and the design wrapper; run synthesis and then File / Export the Hardware (without including the bitstream;) then File / Launch SDK. In SDK, use File / New Application Project and select the Hello World application. After SDK creates (automatically) the ELF file, associate it in Vivado with the design under Tools \ Associate ELF file; finally, in Vivado generate the bitstream and then in the Hardware Manager program the BASYS3 board and observe the UART output with a terminal program. As I said, this seems to work without any problems with the Microblaze MCS but not the Microblaze. Strangely, the Microblaze design does not create any error messages or obvious warnings. Greatly appreciate any insight. Thanks.
  6. emarte

    Problem wih Arty S7-50 mapping I/o Pins

    Hello All! I have a Arty S7-50 Rev B Board. I am trying to control a mobile robot . I am also using a camera and to talk to both of them I need either I2c or serial communication. So far I created my system using microblaze with no problem. I tested leds, buttons, uart communication etc. My problem comes when I try to map pins other than buttons, leds or switch. I haven't been able to put the system to work. I Tried testing all I could think of before coming to the forums. I saved the project as another one, Created a new one from scratch etc etc and nothing so far. It have been many days if not weeks working in this part. I am pretty confidence about my design and about what I have to do with the robot. What I can't not is get signals out. So at this moment I'll give you some print screen of what I have. I could have some mistakes but it have been a lot of copy and paste and change so I got nowhere to go. I hope some of you could point me on where or how to go. I have this system with all this IP but at the beginning I was testing one by one. I need wither 2 uartlite o 1 I2c working. I know the microblaze, gpio0, timer and interrupt is working. Constraints: I had played a lot with this, this is the las I got. ## Switches set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L20N_T3_A19_15 Sch=sw[0] set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L21P_T3_DQS_15 Sch=sw[1] set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=sw[2] set_property -dict { PACKAGE_PIN M5 IOSTANDARD SSTL135 } [get_ports { sw[3] }]; #IO_L6N_T0_VREF_34 Sch=sw[3] ## Buttons set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L18N_T2_A23_15 Sch=btn[0] set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_A22_15 Sch=btn[1] set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L19N_T3_A21_VREF_15 Sch=btn[2] set_property -dict { PACKAGE_PIN H13 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L20P_T3_A20_15 Sch=btn[3] ## Pmod Header JA #//set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { jap }]; #IO_L4P_T0_D04_14 Sch=ja_p[1] set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { led2 }]; #IO_L4P_T0_D04_14 Sch=ja_p[1] ## Pmod Header JD ##//set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jap }]; #IO_L20N_T3_A07_D23_14 Sch=jd1/ck_io[33] set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { tx_1 }]; #IO_L21P_T3_DQS_14 Sch=jd2/ck_io[32] set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { rx_1 }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jd3/ck_io[31] set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { tx_0 }]; #IO_L23N_T3_A02_D18_14 Sch=jd9/ck_io[27] set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { rx_0 }]; #IO_L24P_T3_A01_D17_14 Sch=jd10/ck_io[26] set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { leds[0] }]; #IO_L16N_T2_A27_15 Sch=led[2] set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { leds[1] }]; #IO_L17P_T2_A26_15 Sch=led[3] set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { leds[2] }]; #IO_L17N_T2_A25_15 Sch=led[4] set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { leds[3] }]; #IO_L18P_T2_A24_15 Sch=led[5] ## USB-UART Interface set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_25_14 Sch=uart_rxd_out set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L24N_T3_A00_D16_14 Sch=uart_txd_in ## ChipKit I2C set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_RS0_15 Sch=ck_scl set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_RS1_15 Sch=ck_sda ## Configuration options, can be used for all designs set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property CONFIG_MODE SPIx4 [current_design] ## SW3 is assigned to a pin M5 in the 1.35v bank. This pin can also be used as ## the VREF for BANK 34. To ensure that SW3 does not define the reference voltage ## and to be able to use this pin as an ordinary I/O the following property must ## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being ## used the internal reference is set to half that value (i.e. 0.675v). Note that ## this property must be set even if SW3 is not used in the design. set_property INTERNAL_VREF 0.675 [get_iobanks 34] Schematic Elaborated Design: From what I see eveything it is fine, isn't it ? I/O Pots on Schematic I/O Ports on Synthesized Design Code of Sliding LEDS using timer on LEDS: This is funny, these are some sliding leds. It does not matter where I put / map this pins on contraints, this always light the leds. I was tring to map this in pmod header JD but it just ligh the leds. Serial Test: Here the USB serial workf fine with the PC but the other 2 are sending nothing. I2C selftest. The selftest failed, I know it fails on XIic_SelfTest This board is brand new, I only have it for a few weeks. I havent connected anything to the ports. I measured pins either with a tester or with a analog discovery so not short ciruits or similar have been produced. Any help would be apreciated. Edwin
  7. Hello, I'm trying to configure my Basys 3 board to control a DC motor through the Pmod connector with an HB5 within Vivado. I've followed all steps in the Pmod IP tutorial but I'm stuck at 3.3. I'm not sure which specific pmod ip block I should use or how exactly to connect it. I couldn't find one corresponding to the hb5. Any advice would be greatly appreciated. Additional points: I don't need clocks or interrupts fed to the pmod I'm simply trying to control the operation (on/off) of the motor through one of the on-board switches. Thanks, gd
  8. Hi Everyone, Just accidentally flashed the EEPROM attached to the FT2232 device on the Arty. The board is dead without the USB connection. Been using for 2 months without issues until today. In Vivado it is showing: "ERROR: [Labtoolstcl 44-469] There is no current hw_target.". when trying to Auto Connect with the target in Hardware Manager. Within FT_Prog (FTDI's flash tool), the registers (e.g. serial number, vendor ID, D2XX/VCP driver ...) can all be read and modified. How can it be restored back to Digilent factory setting? Is there an FT_Prog template that we can use? Thanks, Robin
  9. We are suppose to add a library from here: https://github.com/Digilent/vivado-library/releases and add it to the projects IP repository list to be able to add the block in the IP Integrator. I have checked all the releases and i cant find the Pmod NIC100 anywhere, i think its called PmodNIC, but correct me if am wrong because i haven't seen it anywhere anyway. Until i find this IP, the Pmod is just another paperweight on my desk along with my stalled project, Please help. I am using the Arty A7: Artix-7 FPGA Development Board.
  10. Aleksandar

    USB CAM INTERFACING TO ZYBO

    Hello, my friends, i am new here and it is my first project. This project will be my BSC. I have to make next: 1. Make USB CAM interfacing on System Level using systemC... My diagrams are shown in the post. I need to capture the photo using a USB CAM. After that, the picture needs to be stored in some memory. After that the image processing logic (In my case, the logic needs to have the photo (stored in memory) as its input, the idea is just to decrease the photo size (pixels) and the output is the result (decreased size picture)), after that the result of processing needs to be stored in memory too. After that i have to choose... in easier way i will use some photo viewer to see the result, in more difficult way i will use HDMI in order to see my result on the HDMI enabled monitor. My plan is making it on System Level using coding, HLS,IP integrator, SDK for some software. 2.If SystemLevel work great i need to make it on RTL, IP level using pure HDL. I will use Vivado. I am not sure for now what i need to modify from SystemC to IP level (For now, i think just Image processing logic). 3.IP verification using QuestaSim. I have a question: 1. Has someone done something similar? Can you help me, like as give me some good literature or example (For now i am focusing on USB interfacing, i have been searching about this about few days, but without results..., I have read a book (SystemC "From Ground up")). 2. All suggestions are welcome Best regards!
  11. yorees11

    Interrupts Not Working in Microblaze

    Hi all, I have been working with the CMOD A7 board using vivado 2018 and sdk. I have been trying to get the microblaze soft core to respond to the interrupts generated by the peripherals. I started with the timer but have since moved simpler to the uart. I have connected my hardware as shown here. And the code that I am testing is an imported example from drivers board support package. Specifically, it is the one from the uartlite and it is the interrupt exapmle. /****************************************************************************** * * Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * Use of the Software is limited solely to applications: * (a) running on a Xilinx device, or * (b) that interact with a Xilinx device through a bus or interconnect. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Except as contained in this notice, the name of the Xilinx shall not be used * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * ******************************************************************************/ /******************************************************************************/ /** * * @file xuartlite_intr_example.c * * This file contains a design example using the UartLite driver (XUartLite) and * hardware device using the interrupt mode. * * @note * * The user must provide a physical loopback such that data which is * transmitted will be received. * * MODIFICATION HISTORY: * <pre> * Ver Who Date Changes * ----- ---- -------- ----------------------------------------------- * 1.00a jhl 02/13/02 First release * 1.00b rpm 10/01/03 Made XIntc declaration global * 1.00b sv 06/09/05 Minor changes to comply to Doxygen and coding guidelines * 2.00a ktn 10/20/09 Updated to use HAL Processor APIs and minor changes * for coding guidelnes. * 3.2 ms 01/23/17 Added xil_printf statement in main function to * ensure that "Successfully ran" and "Failed" strings * are available in all examples. This is a fix for * CR-965028. * </pre> ******************************************************************************/ /***************************** Include Files *********************************/ #include "xparameters.h" #include "xuartlite.h" #include "xintc.h" #include "xil_exception.h" #include "xil_printf.h" /************************** Constant Definitions *****************************/ /* * The following constants map to the XPAR parameters created in the * xparameters.h file. They are defined here such that a user can easily * change all the needed parameters in one place. */ #define UARTLITE_DEVICE_ID XPAR_UARTLITE_0_DEVICE_ID #define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID #define UARTLITE_INT_IRQ_ID XPAR_INTC_0_UARTLITE_0_VEC_ID /* * The following constant controls the length of the buffers to be sent * and received with the UartLite device. */ #define TEST_BUFFER_SIZE 100 /**************************** Type Definitions *******************************/ /***************** Macros (Inline Functions) Definitions *********************/ /************************** Function Prototypes ******************************/ int UartLiteIntrExample(u16 DeviceId); int SetupInterruptSystem(XUartLite *UartLitePtr); void SendHandler(void *CallBackRef, unsigned int EventData); void RecvHandler(void *CallBackRef, unsigned int EventData); /************************** Variable Definitions *****************************/ XUartLite UartLite; /* The instance of the UartLite Device */ XIntc InterruptController; /* The instance of the Interrupt Controller */ /* * The following variables are shared between non-interrupt processing and * interrupt processing such that they must be global. */ /* * The following buffers are used in this example to send and receive data * with the UartLite. */ u8 SendBuffer[TEST_BUFFER_SIZE]; u8 ReceiveBuffer[TEST_BUFFER_SIZE]; /* * The following counters are used to determine when the entire buffer has * been sent and received. */ static volatile int TotalReceivedCount; static volatile int TotalSentCount; /******************************************************************************/ /** * * Main function to call the UartLite interrupt example. * * @param None * * @return XST_SUCCESS if successful, XST_FAILURE if unsuccessful * * @note None * *******************************************************************************/ int main(void) { int Status; /* * Run the UartLite Interrupt example, specify the Device ID that is * generated in xparameters.h. */ Status = UartLiteIntrExample(UARTLITE_DEVICE_ID); if (Status != XST_SUCCESS) { xil_printf("Uartlite interrupt Example Failed\r\n"); return XST_FAILURE; } xil_printf("Successfully ran Uartlite interrupt Example\r\n"); return XST_SUCCESS; } /****************************************************************************/ /** * * This function does a minimal test on the UartLite device and driver as a * design example. The purpose of this function is to illustrate * how to use the XUartLite component. * * This function sends data and expects to receive the same data through the * UartLite. The user must provide a physical loopback such that data which is * transmitted will be received. * * This function uses interrupt driver mode of the UartLite device. The calls * to the UartLite driver in the handlers should only use the non-blocking * calls. * * @param DeviceId is the Device ID of the UartLite Device and is the * XPAR_<uartlite_instance>_DEVICE_ID value from xparameters.h. * * @return XST_SUCCESS if successful, otherwise XST_FAILURE. * * @note * * This function contains an infinite loop such that if interrupts are not * working it may never return. * ****************************************************************************/ int UartLiteIntrExample(u16 DeviceId) { int Status; int Index; /* * Initialize the UartLite driver so that it's ready to use. */ Status = XUartLite_Initialize(&UartLite, DeviceId); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* * Perform a self-test to ensure that the hardware was built correctly. */ Status = XUartLite_SelfTest(&UartLite); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* * Connect the UartLite to the interrupt subsystem such that interrupts can * occur. This function is application specific. */ Status = SetupInterruptSystem(&UartLite); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* * Setup the handlers for the UartLite that will be called from the * interrupt context when data has been sent and received, specify a * pointer to the UartLite driver instance as the callback reference so * that the handlers are able to access the instance data. */ XUartLite_SetSendHandler(&UartLite, SendHandler, &UartLite); XUartLite_SetRecvHandler(&UartLite, RecvHandler, &UartLite); /* * Enable the interrupt of the UartLite so that interrupts will occur. */ XUartLite_EnableInterrupt(&UartLite); /* * Initialize the send buffer bytes with a pattern to send and the * the receive buffer bytes to zero to allow the receive data to be * verified. */ for (Index = 0; Index < TEST_BUFFER_SIZE; Index++) { SendBuffer[Index] = Index; ReceiveBuffer[Index] = 0; } /* * Start receiving data before sending it since there is a loopback. */ XUartLite_Recv(&UartLite, ReceiveBuffer, TEST_BUFFER_SIZE); /* * Send the buffer using the UartLite. */ XUartLite_Send(&UartLite, SendBuffer, TEST_BUFFER_SIZE); /* * Wait for the entire buffer to be received, letting the interrupt * processing work in the background, this function may get locked * up in this loop if the interrupts are not working correctly. */ while ((TotalReceivedCount != TEST_BUFFER_SIZE) || (TotalSentCount != TEST_BUFFER_SIZE)) { } /* * Verify the entire receive buffer was successfully received. */ for (Index = 0; Index < TEST_BUFFER_SIZE; Index++) { if (ReceiveBuffer[Index] != SendBuffer[Index]) { return XST_FAILURE; } } return XST_SUCCESS; } /*****************************************************************************/ /** * * This function is the handler which performs processing to send data to the * UartLite. It is called from an interrupt context such that the amount of * processing performed should be minimized. It is called when the transmit * FIFO of the UartLite is empty and more data can be sent through the UartLite. * * This handler provides an example of how to handle data for the UartLite, * but is application specific. * * @param CallBackRef contains a callback reference from the driver. * In this case it is the instance pointer for the UartLite driver. * @param EventData contains the number of bytes sent or received for sent * and receive events. * * @return None. * * @note None. * ****************************************************************************/ void SendHandler(void *CallBackRef, unsigned int EventData) { TotalSentCount = EventData; } /****************************************************************************/ /** * * This function is the handler which performs processing to receive data from * the UartLite. It is called from an interrupt context such that the amount of * processing performed should be minimized. It is called data is present in * the receive FIFO of the UartLite such that the data can be retrieved from * the UartLite. The size of the data present in the FIFO is not known when * this function is called. * * This handler provides an example of how to handle data for the UartLite, * but is application specific. * * @param CallBackRef contains a callback reference from the driver, in * this case it is the instance pointer for the UartLite driver. * @param EventData contains the number of bytes sent or received for sent * and receive events. * * @return None. * * @note None. * ****************************************************************************/ void RecvHandler(void *CallBackRef, unsigned int EventData) { TotalReceivedCount = EventData; } /****************************************************************************/ /** * * This function setups the interrupt system such that interrupts can occur * for the UartLite device. This function is application specific since the * actual system may or may not have an interrupt controller. The UartLite * could be directly connected to a processor without an interrupt controller. * The user should modify this function to fit the application. * * @param UartLitePtr contains a pointer to the instance of the UartLite * component which is going to be connected to the interrupt * controller. * * @return XST_SUCCESS if successful, otherwise XST_FAILURE. * * @note None. * ****************************************************************************/ int SetupInterruptSystem(XUartLite *UartLitePtr) { int Status; /* * Initialize the interrupt controller driver so that it is ready to * use. */ Status = XIntc_Initialize(&InterruptController, INTC_DEVICE_ID); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* * Connect a device driver handler that will be called when an interrupt * for the device occurs, the device driver handler performs the * specific interrupt processing for the device. */ Status = XIntc_Connect(&InterruptController, UARTLITE_INT_IRQ_ID, (XInterruptHandler)XUartLite_InterruptHandler, (void *)UartLitePtr); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* * Start the interrupt controller such that interrupts are enabled for * all devices that cause interrupts, specific real mode so that * the UartLite can cause interrupts through the interrupt controller. */ Status = XIntc_Start(&InterruptController, XIN_REAL_MODE); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* * Enable the interrupt for the UartLite device. */ XIntc_Enable(&InterruptController, UARTLITE_INT_IRQ_ID); /* * Initialize the exception table. */ Xil_ExceptionInit(); /* * Register the interrupt controller handler with the exception table. */ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)XIntc_InterruptHandler, &InterruptController); /* * Enable exceptions. */ Xil_ExceptionEnable(); return XST_SUCCESS; } The problem is that the code gets stuck in the while loop (as it did with the other interrupt examples) and is always waiting for the interrupt. In either case the event that triggers the interrupt has occurred and the interrupt signal goes high but the controller never acknowledges the interrupt nor runs the handler. I am needing some help as to what is going wrong here and I'm not sure if its the hardware or software. Thanks,
  12. Hi All, I have recently downloaded Vivado 2018.2 and begun playing around with CMOD A7 35T. I did the the blinky tutorial and then just finished Cmod A7 Programming Guide. At the end of which, I programmed the button project into the flash memory of the device. I then disconnected the device and plugged it back in to verify the code was loaded onto the device on startup. The code indeed loaded and I can light the LEDs with the corresponding button; however, now my host pc cannot find the target device anymore. I tried restarting Vivado and plugging and unplugging the FPGA board and nothing seems to get it to show up in the hardware manager wizard or autoscan. I'm pretty new to FPGA programming so I could use some help to get my board reconnected and the program in Flash erased. Thanks
  13. AdamZ

    Nexys Video No Hardware Target Exists

    I am trying to operate the Nexys Video development board using the vivado hardware manager on a windows 8 system. However I keep getting No hardware targets exist on the server error. Steps i have taken to remedy the situation include: Re-installed Vivado with included cable drivers Tried different versions of vivado Tried on a different PC Formatted PC and installed vivado Updated FTDI drivers Tried 3 different (new) USB cables Installed cable drivers manually The programming jumper is in the right position (jtag), the USB cable is plugged into the correct (prog) port and the board is powered. Can anyone suggest anything else I might try to fix the issue? Thanks.
  14. I've created a block ram generator(single port ROM) in vivado using a coe file in verilog. I'm able to read the values one at time using continuous statement(able to instantiate rom block once a clock pulse). Here is my snippet: module coedata(clk,rst,a); input clk,rst; output [31:0]a; wire[12:0]addra,out; wire [31:0]douta ; count c1(clk,rst,out); // just gives count in 'out' to access address(addra) assign addra=out; blk_mem_gen_0 your_instance_name ( .clka(clk), // input wire clka .addra(addra), // input wire [12 : 0] addra .douta(douta) // output wire [31 : 0] douta ); assign a=douta; endmodule This is ok. I can read value through instantiating once a clock. But I want to store all these values into 2D wire such as [31:0] a[0:100].I want all the values to be available in one clock pulse.(Just assume we have created a sufficient ROM block) module coedata(clk,rst); input clk,rst; reg [31:0]a[0:99]; wire[12:0]addra,out; wire [31:0]douta ; count c1(clk,rst,out,i); // just gives count in 'out-binary' to access,'i-integer' address(addra) assign addra=out; blk_mem_gen_0 your_instance_name ( .clka(clk), // input wire clka .addra(addra), // input wire [12 : 0] addra .douta(douta) // output wire [31 : 0] douta ); assign a=douta; endmodule It is saying that 'i' is not a constant. Thanks in advance.
  15. Hello, I want to use the AXI IIC bus Interface found in Vivado to read data from several MLX90393 sensors. My question is about the amount of AXI IIC interfaces needed for this. Is it enough to use only one, or is it necessary to use one for each sensor that will be used? Thanks in advance. MLX90393-Datasheet-Melexis.PDF
  16. I have created a design in Vivado where I have used XADC with Zynq-7000 processor for acquiring a sine wave applied to the auxillary input of XADC. Now I have exported my hardware along with the bitstream file to the SDK. Now I want to create an application project in C/C++ for the corresponding design. I am facing problem in which header files to include and how to configure the code for proper implementation. Please help with the above issue.
  17. Caleb

    Im completely new to this

    Hi, I'm just getting into programming FPGAs and I've made my first program "blinky light" but I cant get my computer to either find the FPGA when connected or I'm missing a step when I set up Vivado. I've ran the Synthesis, Implementation, and generated the bitstream and everything completed without any errors. I just need to know how to do last part which is to put the code on the FPGA. Thanks! What I'm using/running: Ubuntu 18.04 (OS on my computer), Vidado WebPack, Arty A7 35t, and if it helps I programmed it in Verilog
  18. mmmtgo

    unable to connect to hw_server

    this is my first attempt to program an FPGA (I use Basys 3), and when I tried to connect to the hw_server after generating the bitstream , I got this error:
  19. Abhinav Airan

    Pmod GPS not working

    I am using a pmod GPS with a zybo z7-10 board. However, even after running the sample code for the GPS, nothing is being printed on the serial monitor. I'm not entirely sure whether I have connected the pmod right, since there are 6 pins on the GPS but 12 pins on the pmod port. Nowhere has anyone mentioned whether one should connect the pmod GPS on the top six pins or the bottom six pins. Am I doing something wrong here or is there some other problem? I have also attached a picture of my block diagram for reference.
  20. smit

    Measuring time using a Zynq Processor

    I am working on the Zybo Z7-10 board. My goal is to determine the position and orientation of the FPGA in space at any given instance. For that, I am using a PmodACL2 and PmodGYRO. Now, I need to integrate the accelerations and angular velocities. How do I measure the time at which the Pmods are giving me the data?
  21. I've gone through Getting Started with the Vivado IP Integrator https://reference.digilentinc.com/vivado/getting-started-with-ipi/start. Now I want to insert my own blocks into a block diagram, so I can create designs that use both the FPGA fabric and the on-chip ARM cores on my Arty Z7 board. Below is a block diagram and the Verilog code for "myblock". I want to insert myblock in the connection between axi_gpio_1 and rgb_led so I can do some transformations on those signals. How can I determine the "data type" of the ports of axi_gpio_1 and rgb_led, and how can I modify myblock.v so its ports are compatible and I can connect myblock between axi_gpio_1 and rgb_led? A more general question: what would you recommend as a next level of tutorial to study so that I wouldn't have to ask the questions above? I've looked on the Xilinx site, but the amount of documentation is overwhelming. I don't know where to start! Here is myblock.v and part of my block diagram:
  22. fefernandezpy

    partial reconfiguration with nexys4

    Hi. I use nexys4 with vivado for do partial reconfiguration. After several test the open hardware manager lost comunication with nexys4. I can load simple .bit files and files of partial reconfiguration using PlanAhead, but I can not down again files using vivado. The same happened with 2 board nexys4. ¿What can I do?
  23. Nachiket Karve

    Connect two Pmods to the same port

    I recently started working on the zybo z7-10 board. I have two pmods - the PmodGPS and the PmodCON3. Both of these pmods have 6 pins each and I want to connect both of these pmods to the same port on the fpga. However, I could not connect the PmodGPIO_0 and the PmodGPS_0 blocks to the same port in my Block Design in Vivado. Is there any way to do this?
  24. I'm about to install Vivado on a new computer and want to know which version(s) will work for compiling the Arty Z7 and Arty A7 example projects. I'm asking because I've tried to use version 2017.4 twice and had problems each time, possibly due to version incompatibility problems. Using version 2016.4 resulted in success each time. In another thread, @jpeyron said "The xadc project was made for Vivado 2016.4. Unfortunately, the version does matter." Unfortunately, the "Installing Vivado and Digilent Board Files" document https://reference.digilentinc.com/vivado/installing-vivado/start (which is referenced at https://reference.digilentinc.com/reference/programmable-logic/arty/start?redirect=1, https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start, https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start, and probably lots of other project "start" pages) recommends using "Vivado Design Suite - HLx Editions - 2017.4 Full Product Installation"! So, does the 2017.4 HLx edition work with the Arty Z7 and A7 example projects? If not, the "Installing Vivado and Digilent Board Files" document contains bad advice, which can lead to users wasting hours or days of their time downloading and installing the software and then trying to get the projects to work. Please clarify which Vivado versions and Editions (plain Vivado vs. HLx) work with the example projects.
  25. Hello, I am currently following the first tutorial of the Zynq Book using the Zybo board and I am t the part where I am to launch the SDK after exporting hardware and receive the following error after the SDK loads up: 'Importing Hardware Specification' has encountered a problem. An internal error occurred during: "Importing Hardware Specification". java.lang.NullPointerException. Attached is a screenshot of the error. Thank you for any help.