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Found 32 results

  1. Hi every one. I was Created HLS Ip Core. This Core is a simple Image Filer, and the input for this Core is a matrix of picture that I built in Matlab, Now I'm trying to have a input from HDMI and filter output from VGA. In other words, I don't know "How create a simple block design in ZYBO for have HDMI input, VGA output and HLS IP CORE?" and "Which commands need to read frames from input in SDK sowftware?" Best regards. Abish SJ
  2. I'm having Genesys 2 Kintex 7 board.. i want to display image via VGA from block Ram. I stored pixel value (gray scale) in Block Ram and size of images is 100 * 100 and represent as 8 bits.. Is there is any example?? suggestion?
  3. Hi everybody I want to show my project connected with Jumping-Jack game from 1983. I created it for my dissertation to graduate engineer studies on my university. Although it was created originally for Altera DE1 it can be easily ported on any Xilinx device (it was tested on Artix-7 too with big success). The only difference is that in this case you have just to change PLL component to DCM one to achieve apprioprate graphic clock rate - the rest of project is not needed to change. It runs on 1280x1024, 60 Hz - the ratio is not important - it looks fine both on 4:3 and 16:9. The project is written in VHDL. Here are photos from my project (the game is shown on Samsung panoramic LCD monitor from 2007): Here is the link to the package with .vhd files to project: NOTE: it is not ideal but it is playable If any questions write to me on the following e-mail adress: Greetings, Jacob
  4. ivan

    Nexys3 VGA output

    Hello everyone. I'm currently trying to create simple VGA EDK project to show something on the LCD monitor with Nexys3 board. Nexys3 board has Micron celular RAM and I have a problem that every row is represented by four same rows on the screen. I think that my problem is like problem described on Xilinx Community forum: I've used PLB bus and tried setting Video Memory on base address of Micron RAM and on high addres - 2 MB. I have also tried to set Video Memory to whole Micron RAM (16 MB). Micron RAM was successfully tested with the SDK built in memory test. For software code, I used example from Xilinx (xtftexample.c). I think that problem is with speed of Micron RAM. I found that in asynchronus mode you need to wait 70 ns for data to be ready. This means that frequency of accessing to Micron RAM is about 14.29 MHz and TFT controller works with clock of 25 MHz. Does anyone have example EDK project which uses Micron RAM in synchronous mode? If you need any information about my project, please let me know. I would appreciate any help.
  5. Hi, I'm hoping to PWM an extra bit(s) out of the LSB of the VGA DAC on the Neyx4ddr board so I'd like to know what kind of bandwidth the VGA DAC has. On the schematic it has a 4k resistor, but what's the capacitance ?
  6. iGary

    NEXYS4: VGA BMP Overlay

    I apologize if I'm asking a question with an obvious answer but web searches and forum searches weren't helpful. I've recently started looking at the Nexys4's VGA output. And I'm using the User Demo Source for ISE 14.7 for reference. I'm intrigued by the simplicity of the method used to generate the on-screen images from a memory overlay. But I haven't found any documentation of how the COE file was generated from the original BMP file. Is the method documented and/or is there a utility for converting BMP files into a COE compatible format? Thanks
  7. Hello everyone . I am looking for FPGA development boards that offers the following ports VGA PS/2 Two DB9 RS232 RJ45 i also need an SMA Connector and at least 1600K gates so Spartan 3E Starter Board is not an option for me, can anyone kindly advise me about the board I should go for ,and what Pmod modules should I purchase with it. Regards, Abdul Hafeez.