Search the Community

Showing results for tags 'usb-uart'.

More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL







Found 1 result

  1. Hi, sorry if I'm making a very basic question; I want to use a uart protocol to send data to-from a PC, using the j11 USB/UART-JTAG connector on a Zybo Zynq7000. Simply put, my problem is that I don't know where to map the tx/rx wires. In other boards it is clear which pins I should use. In the zynq-7000, the Zybo-Master.xdc file does not have these (only clock, PMODs, leds, switches and buttons). From the zybo Reference manual (page 12), MIO48 and MIO48 are the 1.8V tx-rx pins that receive the serial data converted from the USB packets through the FT2232HQ USB-UART bridge. The problem is that I cannot access those pins. My source is a simple, generic UART code in verilog. I'm using VIVADO. I've tried to create a Block design, enabling the UART1 on the ZYNQ7 Processing System and exporting the xdc file, but apparently it is forbidden to place any wire on the C12 and B12 sites (the physical pins for the MIO 48&49, if I understood correctly. Essentially what I need is a tutorial to create a project in verilog to communicate via the serial port available at the USB bridge. Thanks for any help, Miguel