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Found 23 results

  1. Hello all, I bought the nexys 100T , and since I am new I started with the basic tutorial blinky. Everything goes well until I get to step 8. "Synthesis, Implementation, and Bitstream Generation" The Synthesis ran successfully, and where it fails is at the bitstream generation. Since the Synthesis was completed I am assuming is not the verilog code, and is just some setting that I need to complete. The log gives the following in "Message:" (attached) Please help this is like the most frustrating hello world I ever had to do. I attached my project files and constrain files in case anyone wants to look at it. blinky.xpr Nexys-A7-100T-Master.xdc
  2. Hi all: I'm new to both Vivado and the Basys3 board. I've been working thru the initial tutorials to get myself familiar with the software and the board. The very 1st tutorial, Getting Started with Vivado, went fine. Everything worked as advertised. The problem I've run into is with the 2nd tutorial, Basys 3 Programming Guide Tutorial ( I have the latest version of Vivado (2018.3) and the tutorial was built with 2015.1. The tutorial even has a zip file to download both the sw_led.v file and a Basys3_sw_Demo.xdc constraint file. After downloading the files, building the project, then running the synthesis I get 26 critical warnings that cause the Implementation and Generate BitStream to fail. 22 of the critical warnings are "V17 is not a valid site or package pin name" (and each of the following 21 warnings change the "V17" to the next pin name in the constraint file. (I've checked the schematic and the Pin Names ARE VALID) The next critical warning is "Setting property "IOSTANDARD' is not allowed for GT Terminals and this error is flagging only a single line in the constraint file yet ALL of the switches in the constraint file all do a "set_property IOSTANDARD LVCM0S33......... The final 2 critical warnings are "Cannot set LOC property of ports. Site location is not valid. This error is flagging two of the LED settings in the contraint file yet, once again, all 16 of the LED's are using the same commands within the constraint file. I'm at a brick wall trying to figure out what the heck the problem is here. As I said...the 1st Tutorial went fine. This tutorial even included the constraint file needed for the project. I've attached a zip file containing the entire Vivado project. Any help/advice would be greatly appreciated. THANKS!
  3. I am going through the Zynq Book Tutorial, version 1.3 April 2014. It seems the Zynqbook and Zynqbook Tutorial are leveled at Vivado 2014.x Zedboard and I have Vivado 2017.2 and Zybo Z4-20 board. Following example 1.B for the Zedboard, the tutorial states on page 15, "Click Run Connection Automation from the Designer Automation message at the top of the Diagram window and select /axi_gpio_0/GPIO." Then a dialog box labeled "Run Connection Automation" will appear. In my version of VIvado or Zybo constraints I don't get this popup window or a selection the looks like /axi_gpio_0/GPIO and now am at a loss on how to connect the AXI GPIO and LEDs. Is there a newer version of this book that includes the Zybo Z7-20 series? Thanks in advance.
  4. I've gone through Getting Started with the Vivado IP Integrator Now I want to insert my own blocks into a block diagram, so I can create designs that use both the FPGA fabric and the on-chip ARM cores on my Arty Z7 board. Below is a block diagram and the Verilog code for "myblock". I want to insert myblock in the connection between axi_gpio_1 and rgb_led so I can do some transformations on those signals. How can I determine the "data type" of the ports of axi_gpio_1 and rgb_led, and how can I modify myblock.v so its ports are compatible and I can connect myblock between axi_gpio_1 and rgb_led? A more general question: what would you recommend as a next level of tutorial to study so that I wouldn't have to ask the questions above? I've looked on the Xilinx site, but the amount of documentation is overwhelming. I don't know where to start! Here is myblock.v and part of my block diagram:
  5. Here my experience with the Cmod A7-35T evaluation board and the MMCM module, take a look and report me if I've to chage somethings, hope it can help. Due to the size of the document (3.5 Mb due to lot of screenshoot) I've to put this one for downloading from my dropbox, for this reason I kindly ask to some admin to let me know if I can or not put inside a download link to my dropbox folder in order to share the tutorial. Thank Best regards
  6. Hi I have a general question about how to try out tutorials, demos, and just how to look at a project folder. When I open a tutorial/demo/project that I download from github, I always see a bunch of folders with the same names: hw_handoff, proj, repo, sdk, src, among other things. Can someone please explain these names, and maybe names of other folders that I may see in other projects? Are the contents of these folders dependent on each other? Can I implement the project with just one? How do I use these folders? Thanks
  7. Colin

    Zybo tutorial help

    i currently have a project where i need to produce a tone from a zybo board and to familiarise myself with the board i downloaded the pdf from and the zip files but and i do the tutorials step for step but when i try to run the programme on the board nothing happens im using vivado 2017.1 i have the ports set to 115200 baud when i import the c code i get a warning from xparamaters.h i asked my project manager and they said its because im not using costraints but the turtorial specifically mentions not using constraints can anyone tell me what am i doing wrong despite the fact im doing the tutorial step for step?
  8. Zygot goes back to the future to transfer data between two FPGA boards at 600 MB/s. Along the way he has a debugging adventure, learns ( AGAIN!!! ) why free stuff rarely is free and remembers when Digilent made FPGA boards that were great for development projects. This is a nice project for beginners or old hands to read through even if you don't have the hardware. CAUTION!!! You must read through the README text file before trying to replicate this project in hardware. Release 2 fixes some bad commentary in the source files and improves the behaviour of the UART transmitter
  9. So, I just received my Digital Discovery earlier this week. I've actually got a project coming up where I'll be able to make use of it, so thought I'd familiarize myself with the differences between it and the Analog Discovery. I proceeded to walk through the protocol tutorial that uses the ALS PMOD to demonstrate SPI interaction. I had never tried this with the AD2, and figured it would be a good test. Unfortunately, after checking my work multiple times, I was still only getting back 0 signals. Thinking the problem could be the DD, I tried the same thing on the AD2 with the same results. After scratching my head a few times, it occurred to me that the prescribed pin assignments looked strange. The tutorial says CS is assigned clock, and SCK is assigned to select. I went and double checked my hunch in the ALS docs, and indeed there was the problem. The tutorial incorrectly swaps these two pins. CS is (chip) select, and SCK is (serial) clock. Once I swapped the pins, all was well. Just and FYI for the content team and others who might face the same issue. Dave
  10. I am walking through the Getting Started With Zynq tutorial and am at a crossroads in the design. In step 5.2) of the tutorial: "After the design validation step we will proceed with creating a HDL System Wrapper. In the block design window, under the Design Sources tab, right-click on the block diagram file. We labeled it “” and select Create HDL Wrapper." Vivado gives me a pop up with two options and the tutorial doesn't provide any guidance. If I were not so new to FPGA design maybe the answer would be clear as day but as a beginner I wish these detail were more clear. Copy generated wrapper to allow user edits Let VIvado manage wrapper and auto-update The window also states;"You can either add or copy the HDL wrapper file to the project. Use copy option if you would like to modify this file." The next step moves on to generate a bitstream file so I'm going to assume that this file will not be edited any longer. I wish the tutorial would provide a bit more context to the steps laid out and how the operations used in this simple project would/could be used in another project. So far I appears that once I'm done this this tutorial I will only have learned how to accomplish the same task, only with a bit more confidence. After step 6 I am given another window the tutorial does not make any mention of. The window is titled Launch Runs with text; "Launch the selected synthesis or implementation runs." and provides 3 choices. Launch runs on local host: Generate scrips only Number of jobs [2] {with option to change value} There is also a choice of Launch directory. On this one I'm totally clueless. I realize that Diligent is not responsible for changes in the Vivado IDE but I as a company focused on education I think it could do better on updating tutorials to accurately reflect the changes in Vivado. I would also LOVE to see more Zybo tutorials, they are far and few between on the net. The book is alright but a bit difficult to navigate to topics the relevant for beginners. If anyone could respond with instruction on how I SHOULD have proceed with these options and what any of these options really mean I would appreciate it, as I have now come across some warnings in the TCL console about needing a "AXI BFM license to run".
  11. Good afternoon I am learning to use VHDL. I have a Nexys 4 ddr and a PmodSD card, that I would like to learn to use. I downloaded the most recent version of VIVADO, and Xilinx as well. Do you all have a program that I can use, to see how it works or a tutorial to process images? I would appreciate it. Thank you. Kind regards.
  12. Hi every one. I was Created HLS Ip Core. This Core is a simple Image Filer, and the input for this Core is a matrix of picture that I built in Matlab, Now I'm trying to have a input from HDMI and filter output from VGA. In other words, I don't know "How create a simple block design in ZYBO for have HDMI input, VGA output and HLS IP CORE?" and "Which commands need to read frames from input in SDK sowftware?" Best regards. Abish SJ
  13. Hello guys, this question is aimed primarily at Digilent staff but if anyone has an answer, I'm not choosy :-) I just got a CMOD A7 and I'm bringing it up by going through simple projects and tutorials. I'm stumped by this one : I've followed it to the letter, but reality diverges from the internet at step 13. There is nothing in my SDK's "Run As" menu. Why is that, and how can I fix this ? The whole tutorial never mentions the reset signal : how is it generated ? JTAG only ? Also, whenever I upload any bitstream to the FPGA, I get this message : WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. I've tried everything to appease Vivado but to no avail. I get this message even with this tutorial, yet it's never mentioned in any tutorial. Google wasn't any help. Could this be somehow related to my troubles in SDK ? I'm using Vivado 2016.1. Not to criticize, but a tutorial should "just work", otherwise there's not much point to it. Here I have several instructions I need to "interpret", for example, step 11 : "Make sure that the Cmod A7 is (...) connected to the host PC via both the JTAG USB port and the UART USB port." I see two COM ports when I plug the module in, but there's no way to tell which is which except trying to open one with Tera Term while Vivado's hardware manager is connected to the module (if it fails, that must be the JTAG). Also, while I understand that JTAG needs to be connected (and it seems to be, since I can program the device) why does to the UART need to be connected too ? And to what ? I tried having the UART connected to Tera Term while programming the FPGA from the SDK. Since the SDK mentions integrating the ELF into the bitstream, I expected at least to get the "Hello World" once the programming was complete, but got nothing. By the way, the module itself works : it runs the default code it ships with, and I do get the RAM test report coming out on the USB UART, so this isn't a hardware problem. I'm using Windows 10 but as far as I can tell this isn't an issue. I hope a good soul out there can spare a moment to help me :-) Edit : I'm going through the tutorial again with a fine-tooth comb. As early as project creation I get this warning : WARNING: [Board 49-26] cannot add Board Part available at C:/Xilinx/Vivado/2016.1/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available Since I've selected the CMOD A7 A35T I don't get why Vivado would show this. I have checked the reset chain, it seems the board file sets button 0 as a reset source, active high, which matches the module's schematics. I don't know what I did differently but this time I got a full "Run As" menu at Step 13. However when I tried to launch the program I got a big error dialog box that told me : "Could not find FPGA device on the board for connection 'Local'." The board had been plugged in ever since I created the project in Vivado... I'll keep looking and update my question if I find anything new. Edit 2 : got a hunch that this last error could be due to some program not closing a COM port properly. So I re-launched the SDK, unplugged / replugged the module to force Windows to close its COM ports, re-programmed the FPGA with its bitstream... and then I tried Step 13 again. The "Run As" submenu was empty again for some reason (does anyone know ?) but "luckily" the System Debugger entry was still available in the Run Configurations dialog box. This time it worked, in that I got "Hello World" on the UART. Still, the whole process kinda smells of voodoo and instability at this point. Can we get clearer instructions in the tutorial ? Or are my problems due to some Windows 10 incompatibility or maybe using the wrong version of Vivado / SDK ?
  14. Hi everyone, I know that the CPLD starter board that features the XC2C256 is deprecated but can someone provide a few links with a "hello world" application? A blink LED or anything to get me started and at least check if I have my toolchain set up properly. Also, I am using xilinx ISE webpack but a few people have mentioned that vivaldo might be a better choice because xilinx doesn't support coolrunner anymore through webpack(?). I see the devices on the device list so I don't understand why I should use vivaldo. Thanks!
  15. Hi all, I am currently doing the Xilinx tutorial to run Linux on my zybo : In the process, I have to get these task done : Bitstream (for the programmable logic portion) System hardware project hdf file My question is : can I use the generate the bitstream and the system hardware project ? If I complete the tutorial with the generated files, will I be able to run linux and use it with the hdmi or vga output, get access to any kind of command prompt? Thanks. Regards, Herrmattoon
  16. Hi, I have a friend who has bought a Basys 3 and has done some great projects in HDL, but he wants to step it up a notch and try something with MicroBlaze. Although I'm willing to help him I don't have the time for it so I thought about sending him some tutorials on MicroBlaze and GPIO using block design and Vivado. The only problem is that there are no coherent tutorials for this and the ones I found to be decent where for EDK. To be clear I'm not looking for a board specific project, all I want is on tutorial which shows a beginner how to use a GPIO with MicroBlaze in Vivado. Do you have something you could recommend or a tutorial which you are working on? Anything compact and simple with MicroBlaze an AXI GPIO some SDK code and steps on how to set it up will be of grate help. Cheers, K
  17. Hello, I just recently bought a zybo board and was following the digilent tutorial and almost finished the getting started project. However, I cannot make the helloworld.c file after launching the SDK. I can still program the PL side, but if I cannot utilize the PS side. SO now I basically have a standard FPGA until I can get this issue resolved. I have been looking through the xilinx forums too and haven't seen a good solution to this problem. here is an example of the console output and a screenshot of the error message that pops up Building file: ../src/helloworld.c Invoking: ARM gcc compiler arm-xilinx-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/helloworld.o" -I../../getting_started_with_ZYBO_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.d" -o "src/helloworld.o" "../src/helloworld.c" make: *** [src/helloworld.o] Error -1073741502
  18. Dear Community. I've recently bought a Zybo Zynq board and i'm having some getting started problems. Im known with both C and VHDL programming before but i've never had such a multi-purpose FGPA, dualcore board before. I tried following some basic tutorials, like: and several youtube led blinks. But I'm experiencing different problems with all of them. My board isnt listed in the Vivado 2015 > new project > boards list I can't find the right settings to get the leds to the GPIO Or when I find a "pre made tutorial led blink" its made on a earlier version of vivado and i can only open it read only, or it edits the files causing errors. I did however get the Xililinux running at the moment ( but thats just copying bootfiles to a sd card) Is there anyone who has a tutorial which is compatible with Vivado2015 and can get me started trying to do some actual programming in this new and unknown environment to me. Any help would be greatly appreciated. And sorry to ask such a question Greetings
  19. gmv

    Nexys4 ddr resource

    Hi, are there some news about nexys4 ddr resource time to release of Embedded Linux Materials and Advanced Microblaze Design with MIG, Ethernet, UART & GPIO ?
  20. I am following the instructions in the Embedded Linux Hands-on Tutorial and got stuck at step #3 in section 4.2. The step #2 is successful with the following output : make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi- xilinx_zynq_defconfig HOSTCC scripts/basic/fixdep HOSTCC scripts/kconfig/conf.o SHIPPED scripts/kconfig/ SHIPPED scripts/kconfig/zconf.lex.c SHIPPED scripts/kconfig/zconf.hash.c HOSTCC scripts/kconfig/ HOSTLD scripts/kconfig/conf # # configuration written to .config # The command in step #3 gives the following error : make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi- scripts/kconfig/conf --silentoldconfig Kconfig make: unrecognized option '--silentoldconfig' Usage: make [options] [target] ... Options: I am using ubuntu 14.04 LTS, with Xilinx SDK version 2015.1. Please help!
  21. Hi guys, I have been writing PC software for the last 15 years and I now wanted to take a shot at FPGA, I have bought myself the basys3 board and installed the viva do software, I followed the instructions for the Digilent abacus demo, this is a simple binary calculater to show some very basic functions, I Immediately noticed this takes aboud 15minutes before the program can be transferred to the basys3, I understand that synthesis takes some time but 15 minutes seems to much for what my patience can handle, taking into account that the abacus is a simple and uncomplex program, what wil it be with something more complex, do you guys think this is normal? the abacus demo can be found here: Download a bit disappoointed johan
  22. Hi there, I recently purchased a Zybo Zynq 7000 development board and have been working through tutorials to familiarize myself with Vivado, IP blocks, etc (not a ton of experience with FPGAs). I have used the base system design included and successfully was able to display images from the HDMI out on the board using an included demo. For the project I have in mind, however, I really want the HDMI port to function as a receive/sink port rather than transmit/source. All the other peripherals configured in the base system design are perfect for my application aside from the HDMI. Is there a way to change the base system design to have the HDMI configured as receive rather than transmit? Or can someone direct me as to how to configure an IP block in Vivado for HDMI receive for the Zybo? I have no experience with Vivado or IP blocks or p cores or what have you, and while I have a basic understanding how the design flow in Vivado,a guide with beginners in mind would be appreciated. This next part may sound dumb, but is just an idea: while looking through the schematic for the HDMI port, it seems that there is an HDMI_OEN pin (hdmi output enable?), and in Vivado a similar block that says HDMI_OEN is present above the IP block for the HDMI TX. Is it as simple as flipping the value on the HDMI_OEN pin? I feel that is too simple too work but just thought I'd include the info anyways in case it is useful or relevant. Thanks, Chris
  23. Does anyone know how I can get the images used in the Bootloader Tutorial (see image below)? The file is located here: Thanks