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Found 83 results

  1. Hello, I am trying to interface MCP3008 with basys 3 using SPI and store the values in a FIFO and transmit the values to PC using UART. Initially, I designed for ADC to convert input waveform and display results by increment or decrements of LED's. The MCP3008 ADC clock is 1.3 MHz clock. This works and led's increment as the amplitude of the input waveform is increased from signal generator . But when i receive through UART and plot on SerialPlot , the signal is distorted please find the code for ADC below: entity ADC is port ( -- command input clock : in std_logic; -- 100MHz onboard oscillator trigger : in std_logic; -- assert to sample ADC diffn : in std_logic; -- single/differential inputs channel : in std_logic_vector(2 downto 0); -- channel to sample -- data output Dout : out std_logic_vector(14 downto 0); -- data from ADC OutVal : out std_logic; -- pulsed when data sampled -- ADC connection adc_miso : in std_logic; -- ADC SPI MISO adc_mosi : out std_logic; -- ADC SPI MOSI adc_cs : out std_logic; -- ADC SPI CHIP SELECT adc_clk : out std_logic -- ADC SPI CLOCK ); end ADC; architecture behavioural ofADC is -- clock signal adc_clock : std_logic := '0'; -- command signal trigger_flag : std_logic := '0'; signal sgl_diff_reg : std_logic; signal channel_reg : std_logic_vector(2 downto 0) := (others => '0'); signal done : std_logic := '0'; signal done_prev : std_logic := '0'; -- output registers signal val : std_logic := '0'; signal D : std_logic_vector(9 downto 0) := (others => '0'); -- state control signal state : std_logic := '0'; signal spi_count : unsigned(4 downto 0) := (others => '0'); signal Q : std_logic_vector(9 downto 0) := (others => '0'); begin -- clock divider -- input clock: 100Mhz --100MHz/1.3MHz = 74/2 -- adc clock: 1.3MHz clock_divider : process(clock) variable cnt : integer := 0; begin if rising_edge(clock) then cnt := cnt + 1; if cnt = 37 then cnt := 0; adc_clock <= not adc_clock; end if; end if; end process; -- produce trigger flag trigger_cdc : process(adc_clock) begin if rising_edge(adc_clock) then if trigger = '1' and state = '0' then sgl_diff_reg <= diffn; channel_reg <= channel; trigger_flag <= '1'; elsif state = '1' then trigger_flag <= '0'; end if; end if; end process; adc_clk <= adc_clock; adc_cs <= not state; -- SPI state machine (falling edge) adc_sm : process(adc_clock) begin if adc_clock'event and adc_clock = '0' then if state = '0' then done <= '0'; if trigger_flag = '1' then state <= '1'; else state <= '0'; end if; else if spi_count = "10000" then spi_count <= (others => '0'); state <= '0'; done <= '1'; else spi_count <= spi_count + 1; state <= '1'; end if; end if; end if; end process; -- Register sample outreg : process(adc_clock) begin if rising_edge(adc_clock) then done_prev <= done; if done_prev = '0' and done = '1' then D <= Q; Val <= '1'; else Val <= '0'; end if; end if; end process; -- LED outputs PROCESS (adc_clock) BEGIN IF (adc_clock'EVENT AND adc_clock = '1') THEN CASE D(9 DOWNTO 6) IS WHEN "0001" => Dout <= "000000000000011"; WHEN "0010" => Dout <= "000000000000111"; WHEN "0011" => Dout<= "000000000001111"; WHEN "0100" => Dout <= "000000000011111"; WHEN "0101" => Dout <= "000000000111111"; WHEN "0110" => Dout <= "000000001111111"; WHEN "0111" => Dout <= "000000011111111"; WHEN "1000" => Dout <= "000000111111111"; WHEN "1001" => Dout <= "000001111111111"; WHEN "1010" => Dout <= "000011111111111"; WHEN "1011" => Dout <= "000111111111111"; WHEN "1100" => Dout <= "001111111111111"; WHEN "1101" => Dout <= "011111111111111"; WHEN "1110" => Dout <= "111111111111111"; WHEN "1111" => Dout <= "111111111111111"; WHEN OTHERS => Dout <= "000000000000001"; END CASE; END IF; -- END IF; END PROCESS; OutVal <= Val; -- MISO shift register (rising edge) shift_in : process(adc_clock) begin if adc_clock'event and adc_clock = '1' then if state = '1' then Q(0) <= adc_miso; Q(9 downto 1) <= Q(8 downto 0); end if; end if; end process; -- Decode MOSI output shift_out : process(state, spi_count, sgl_diff_reg, channel_reg) begin if state = '1' then case spi_count is when "00000" => adc_mosi <= '1'; -- start bit when "00001" => adc_mosi <= sgl_diff_reg; when "00010" => adc_mosi <= channel_reg(2); when "00011" => adc_mosi <= channel_reg(1); when "00100" => adc_mosi <= channel_reg(0); when others => adc_mosi <= '0'; end case; else adc_mosi <= '0'; end if; end process; end behavioural; --much of the code is of credit to micronova electronics. For fifo, I use the Xilinx IP fifo generator with no FWFT working on 100Mhz clock both on write and read sides. FIFO width = 10 Depth = 2046 and tried increasing upto 131072 with no progress. This is my top level code with UART entity top_module is Generic ( PARITY_BIT : string := "none" -- type of parity ); port( clk, rst,trigger,diffn: in std_logic; adc_mosi,adc_clk,adc_cs : out std_logic; adc_miso : in std_logic; channel : in std_logic_vector ( 2 downto 0); wr_uart,uart_clk_en : in std_logic; WriteEn , ReadEn : in std_logic; full, empty : out std_logic; --w_data: in std_logic_vector(7 downto 0); Dout : inout std_logic_vector(9 downto 0); busy : out std_logic; tx,OutVal: out std_logic ); end top_module; architecture structural of top_module is signal fifo_data_out : STD_LOGIC_VECTOR (9 downto 0); component fifo is port ( reset_rtl_0 : in STD_LOGIC; clk_100MHz : in STD_LOGIC; full_0 : out STD_LOGIC; din_0 : in STD_LOGIC_VECTOR ( 9 downto 0 ); wr_en_0 : in STD_LOGIC; empty_0 : out STD_LOGIC; dout_0 : out STD_LOGIC_VECTOR ( 9 downto 0 ); rd_en_0 : in STD_LOGIC ); end component fifo; begin MercuryADC : entity work.ADC port map ( clock => clk, trigger => trigger, diffn => diffn, channel => channel, -- data output Dout => Dout, OutVal => Outval, -- ADC connection adc_miso => adc_miso, adc_mosi => adc_mosi, adc_cs => adc_cs, adc_clk =>adc_clk ); fifo_i: component fifo port map ( clk_100MHz => clk, din_0(9 downto 0) => Dout(9 downto 0), dout_0(9 downto 0) => fifo_data_out(9 downto 0), empty_0 => empty, full_0 => full, rd_en_0 => ReadEn, reset_rtl_0 => rst, wr_en_0 => WriteEn ); uart_trx : entity work.UART_TX Port map ( CLK => clk, -- system clock RST => rst, -- high active synchronous reset -- UART INTERFACE UART_CLK_EN => uart_clk_en, -- oversampling (16x) UART clock enable UART_TXD => tx, -- serial transmit data -- USER DATA INPUT INTERFACE DATA_IN =>fifo_data_out (9 downto 2) , -- input data DATA_SEND => wr_uart,-- when DATA_SEND = 1, input data are valid and will be transmit BUSY => busy -- when BUSY = 1, transmitter is busy and you must not set DATA_SEND to 1 ); end structural; PFA the schematic of my design and waveform as well. input is 650 hz and Vpp= 1.5V; continuous sine wave. My output waveform appears to be distorted. I'm not sure if there has to be a delay incorporated while sampling the input signal or a is the issue between FIFO and UART. When WriteEn signal is asserted on FIFO, the full flag is asserted at the same instant, does that mean the size of FIFO is not enough. Kindly help, any inputs will be appreciated. MCP3008(3).pdf
  2. Hello, I am new to ZYBO board. I am working on a project where I want to control a sensor from my ZYBO board using UART and receive the data from the sensor via SPI. I searched for the reference design, tutorials online to get started with, but I could not find any. Can anyone point me in the right direction where I can refer to and implement my work? THANK YOU. This is my aim as shown below. I want Zybo to be the main host, not my PC.
  3. Hello, i am having trouble using the chipkit uc32 together with the analog shield here : https://store.digilentinc.com/analog-shield-high-performance-add-on-board-for-the-arduino-uno-retired/ When i connect the Shield to my Arduino UNO one samples needs about 10 microseconds witch should be right. Instead if i connect it to the chipKit uc32 it takes about a 150 microseconds. I guess the SPI communication is not working properly but i dont know why. Since i dont know wether the board is the retired version or the newest i thought it might not work if its the old one. Did anybody else have a similar problem or is there a way to find out wether my uc32 is the old or new revision. Thx in advance Edit: I solved the problem. Instead of using the Arduino IDE i switched to MPIDE. Now it works with a sample rate of 1sample / 25 microseconds. There might be a problem with the Additional Board Manager URL for the Arduino IDE. I might take a look at it if i have the time.
  4. Hello, I am trying to get x,y,z axis data from the accelerometer adxl345 using linx in labview. I have managed to do that with I2C protocol, but I want to do it also with SPI protocol in order to achieve greater sampling rate. I have read the adxl345 datasheet but I struggle figuring out to which exact registers I must write so that I can read the datax,y,z registers. I attach my -so far now working- program below, thank you in advance. adxl345spi.vi
  5. Hy, guys, I am using the PmodCLS, and although it is retired now (October 2018), my project is ongoing with 4 of them, using an adapted VHDL demo code from resource center. I am in need of using one 20x4 LCD module instead of the 16x2 I have there. As a first innocent try, I just connected in parallel the 20x4 pins with the 16x2 pins. The 16x2 continue to work, but the 20x4 shows only squares...(contrast and backlight connections are ok). In the demo lookup file it does not seems to have a configuration command for the LCD. Is PmodCLS automatically configured for 16x2? How could I use a 20x4 LCD on PmodCLS? Does anyone have the information about the instructions set of PmodCLS that could be used on a 20x4 LCD? Thanks for your help, Guacamoleroger
  6. Greetings, Is there a toolkit, etc. for use with the AD2 and Labview for I2C or SPI? I would like to monitor and simulate if possible. I have download and looked at both the Waveforms toolkit and AD2 toolkit, but did not immediately see this functionality. I'm guessing no such bundled library exits. Thank you Cheers, JMA
  7. Hi ! I am interested in using the Digital Discovery controlling multiple devices at the same time with different protocols. E.g. I would like to setup the UART on the digital discovery on DIO 28 as TX and 29 as RX while using SPI at the same time on the default setup DIOs as 24/CS, 25/CLK, 26/DQ0/MOSI, 27/DQ1/MISO. Using then I2C on e.g. 31/SCL and 30/SDA and CAN on 36/RX and 37/TX on top of that would be very nice as well. Is this possible from the user interface (which I would prefer) or do I need to create custom code for that?
  8. Hi all, I am working on SPI transceiver with AD2 in master mode. I am using python sample codes provided. transmitting is working fine but in receiving i am able to get the signals on wire but not to the variable in python rgwRX = (c_uint16*1)() while True: dwf.FDwfDigitalSpiSelect(hdwf, c_int(4), c_int(0)) dwf.FDwfDigitalSpiRead16(hdwf, c_int(2), c_int(24),rgwRX, c_int(len(rgwRX))) dwf.FDwfDigitalSpiSelect(hdwf, c_int(4), c_int(1)) print rgwRX[0] I am getting only '0's corresponding signal while receiving tapped on CRO is attached and it is proper but when i try it using Waveforms software it works but i see same signal on wire
  9. Hello, Does PmodSD (https://reference.digilentinc.com/reference/pmod/pmodsd/reference-manual) support SD mode of operation? Is it designed only to work with SPI mode as written in the reference manual? Please let me know Regards, Vinay Shenoy
  10. Hi all, I am working with zybo zync 7010. i am trying to build spi slave using quad spi using sdk example program. but the data is not received. program hangs on at while (TransferInProgress==TRUE) and will never come out of the loop. please help me out.
  11. Trillian

    Bistream Size Quad SPI

    Hi there, I'm trying to program the arty using quad spi and I get the following error: [Writecfgmem 68-4] Bitstream at address 0x00000000 has size 2192012 bytes which cannot fit in memory of size 2097152 bytes. So I'm ~95kb short. Now I wonder what I can try to make my Bitstream smaller. Would I just try to shrink my cpp application?
  12. I desperately want to connect three devices to a Raspberry Pi3 that has a single Pmod HAT Adapter fitted to it. The devices are all SPI types: Pmod AD1 Pmod ISNS20 Pmod TC1 I can only run 2x devices since ports JA(A) and JB(A) both support SPI, but JC(A) does not. Is stacking of Pmod HAT Adapters allowed or can I connect an SPI device directly to the open GPIO pins? I would greatly appreciate any advice! Even if NOPE is an answer...
  13. Hello, I am trying to use the pmod DA4 with my Arty S750 board. I'm aware that Digilent does not offer an IP for interacting with the Pmod, so I took it upon myself to design one. Anyways, things seemed to be going well until I actually tested the DA4. I know that the DA4 uses SPI to communicate, so I programmed the IP to communicate that way, and it does (outputs from the pmod connector correctly seen on an oscilloscope), but every time I connect it to the DAC I can't get much of anything to come out of the channels. I've read through the AD5628 reference manual, but a few things were ambiguous to me. First the commands on table 9. I don't really understand the difference between writing to the register (command 0) and writing to the DAC channel (command 3), and which I should be using for my project. And second, I plan on using an internal voltage, and it says that setting up the internal voltage is the first step. As I have it now, it's the first thing my program does and I'm afraid that the DAC is unable to read this input (maybe I should add a brief delay? I saw a brief delay in the "simon says" code). I know it's been a long post, but any answers or insights on the DA4 or any other part of my post is much appreciated. Thanks, Gill
  14. I'm having trouble getting the SPI1 port working as a slave on the Cmod board. It works fine as a master talking to an Arduino Mini Pro configured as a slave, but not vise versa. I verified that the Arduino Mini configured as a master is working, but I never receive anything in the SPI1BUF on the Cmod. I have tried setting SPI1CON to 0x8000 and 0x8080, but neither worked. Does anyone have sample code that works as a spi slave?
  15. Hi all, I'm having an issue with the FPGA SPI interface I programmed onto my microzed. The issue is that the interface cannot read the data sent back from my slave device! I'm using a SAMA5d3-xplained devboard, and an oscilloscope to measure signals. I made the SAMA return the same buffer it received, only with every byte shifted. So it's a semi-loopback routine. The oscilloscope captures both the correct signal back from the SAMA (every byte divided by 2), AND the signal going into it (out of the MicroZed). However, the spidev_test.c (that seemingly famous SPI testing utility on the torvalds repository (https://github.com/torvalds/linux/blob/master/tools/spi/spidev_test.c) program that I'm using shows one of two things: 1. Either the result is always an error of "SPI transfer timed out" 2. or the value in rx is the same as in tx. That is, even though the SAMA slave is demonstrably (via oscilloscope) returning something else, all the RX buffer gets is the same as was sent via the TX buffer. In fact, I can even disconnect the header that plugs the master to the slave, and this behavior becomes no different. The difference between these two results is simply a matter of removing the 1050th line in drivers/spi/spi.c when building the kernel. It's the call to wait_for_completion_timeout() in the function static int spi_transfer_one_message(struct spi_controller *ctlr, struct spi_message *msg). What I get from this is basically that the spi-xilinx.c driver does not know where to look for the output from the slave (MISO), and it either waits eternally for that output (if the call to wait_for_completion is left intact) OR it doesn't care to look for the data and just fills the rx buffer with the tx buffer. Now I have a very limited understanding of hardware and driver programming, so I'm basically like a blind man in the dark here. I'm adding printk() statements to spi-xilinx.c and spi.c everywhere, and checking their results with dmesg and there's just nothing enlightening (I'm using PetaLinux, and the devices all show up correctly in /dev and /sys). I'm hoping someone more experienced can shine a light on what I'm doing wrong here, or at least point me in the right direction. Attached is my device tree file, plus a screenshot of the hardware design. (the relevant node in the DT is highlighted below) amba_pl { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "simple-bus"; ranges; [email protected] { bits-per-word = <0x8>; compatible = "xlnx,xps-spi-2.00.a"; clock-names = "axi_clk", "spi_clk"; clocks = <0x1 0xf>, <0x1 0xf>; fifo-size = <0x10>; interrupt-parent = <0x4>; interrupts = <0x0 0x1d 0x1>; num-cs = <0x1>; reg = <0x41e00000 0x10000>; xlnx,num-ss-bits = <0x1>; xlnx,spi-mode = <0x0>; [email protected] { compatible = "spidev"; reg = <0x0>; spi-max-frequency = <0x17d7840>; }; }; }; goodVersion1.dts
  16. I am new user of Waveforms 2015 and the Digital Discovery. I want to generate SPI signal and DIOs, to read from multiplexed-CH ADC. According to "Help" on WaveForms, DIO can be set using "DIO." in script for Protocol-SPI. (Help -> Protocol -> 2. SPI -> about Custom mode -> " DIO.: Lets you set(the ones are not declared as SPI signal) and red the digital pins." ) but I can't find its description. So, could I have the example how to use "DIO." in script for Protocol-SPI ? * I'm using WaveForms Ver:3.7.5 32-bit Qt5.6.3 Windows7. Thanks,
  17. Hello, I've got a question on how to sniff SPI data using Analog Discovery with the WaveForms SDK. The following example uses "sync record" which only stores samples on SPI clock or select (rising) edge. This lets you capture SPI data with an average bit rate of around 2MHz. SPI bursts of up to 40MHz are supported but the average rate needs to be lower. DigitalIn_Spi_Spy.py
  18. Dear All, Me and a colleague of mine are facing an SPI timeout issue on a Zynq. We already posted the issue in the Xilinx forum: https://forums.xilinx.com/t5/Embedded-Linux/SPI-transfer-timeout/td-p/833550 but we did not receive any answer, yet. So I would like to ask your help. I am trying to use a TFT LCD screen with the Digilent Artyz7, exploiting the frame buffer. I created a project on Vivado that exports the Zynq PS SPI interface through EMIO. I have already deployed the linux-digilent kernel (v4.4.0) on the Zynq and I am able to see the SPI peripheral under /sys/class/spi_master/spi2.0 (the device tree has been generated using SDK). Thus, as soon as I try to insert the kernel module for the frame buffer support, I get the following error: spi2.0: SPI transfer timed out I attach the images from the logic analyzer: The kernel module of the frame buffer sends the data correctly through the SPI interface before going to timeout state. Any ideas or suggestions regarding this issue? Thanks a lot. Best Regards, Enrico
  19. I'm trying to get the picosoc project working on a CMOD A7. This is a soft-CPU running code directly from an SPI flash chip, hence I want to get access to the N25Q032A13EF440F pins from verilog. Looking at the Schematic and the .xdc file from the board support package, I can find definitions for qspi_cs and qspi_dq[0-4], which are the chip select and data lines respectively. However there is no definition for for the QSPI_SCK net, which connects to the FPGA pins CCLK_0 and IO_L3N_T0_DQS_EMCCLK_14, both of which are not defined in the .xdc file. Is that deliberately so? Cheers Michael Betz
  20. I want to capture UART data and SPI data at the same time in the Logic analyzer of Analog Discovery 2. UART baud is 115.2kHz and SPI is at 8Mhz. when i increase the sample rate, UART data is not captured. and without increasing the sample rate i can not capture SPI data. what is the optimal setting to capture both low frequency and high frequency signals at the same time?
  21. Hello, I just received my AD2, and I really like it! I like the WG and the scope, and while it took me a little while to figure out the Protocol analyzer, it does a pretty good job showing the data. However, at first glance, the SPI protocol handler under the logic analyzer is somewhat limited because it only handles one channel. One could capture four signals by using the logic analyzer and doing the work manually, but I would like to be able to handle all four (or 6) SPI channels in the logic analyzer, too. I have an MCP3208 which requires a command in the first 10 bits, and then in the next 14 bits returns the data on the MISO pin. Is there any way to do this in the logic analyzer? Thanks Matt Gessner
  22. Hi everyone, In this opportunity I want to establish a SPI communication between two PmodACL and a Zedboard, in Vivado software I done it this way: And I got the Bitstream file without any mistake. But how can I do the SDK configuration for read two PmodACL at the same time?
  23. I have a system where I'm using 2 HS2 cables. One is used for SPI control and the other for Jtag. For my SPI interface, I have written a DLL using the ADEPT2 SDK, that allows me to specify the serial number of teh device to connect for SPI. Unfortunately both devices enumerate as device name "jtagHs2" and If I start my Xilinx Viivado Hardware manager before my SPI interface, the Vivado is taking over the device I want to use for SPI. If I start my spi interface first then vivado correctly picks up the HS2 I want to use for JTAG. Is there a way to prevent this, for example can I change the name "jtagHS2" in my SPI interface eeprom? Thanks, Patrick
  24. I am very new to Raspberry pi and I need help regarding my R-Pi and Pmod ACL2 I would just like to test the functionality of the SPI connection and that's it I am not allowed to install any software I should just use the configure terminal I have installed the spi-dev on my R-Pi and I can't seem to find the ACL2 I'm sure I have connected them correctly Pls help Thanks in Advance
  25. Hello, I am attempting to communicate to a Pmod RF2: IEEE 802.15 RF Transceiver with a Basys3 board using the SPI protocol in VHDL. The microchip on the pmod is the MRF24J40. How do I identify the address of the MRF24J40? To my understanding, if I want to write/read a memory location on the MRF24J40, I need to send the address followed by the address of the specific memory location on the MRF24J40. Is it written on the microchip itself? The master and slave SPI modules that I am attempting to use are linked to this post. The documentation for the master and slave links are below. The specification sheets for the pmod and MRF24J40 are included as well. Master: https://eewiki.net/pages/viewpage.action?pageId=4096096#SerialPeripheralInterface(SPI)Master(VHDL)-Transactions Slave: https://eewiki.net/pages/viewpage.action?pageId=7569477 Pmod: https://www.digilentinc.com/Pmods/Digilent-Pmod_ Interface_Specification.pdf MRF24J40: http://ww1.microchip.com/downloads/en/DeviceDoc/39776C.pdf Thank you. spi_slave.vhd spi_master.vhd