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Found 4 results

  1. xinx_92

    Arty S7 with Simulink

    xinx_92 posted a question in FPGA

    Hello there, I´m not really new to FPGA because I'm used to program Xilinx FPGAs via System Generator on dSpace platforms. However I'm really new with out-of-the-box FPGA programming. I got myself an ARTY S7 development kit and i figured maybe it's also "easy" to deploy my Simulink models via Systems Generator on These FPGAs. But unfortunately I have no idea where to start. Does someone of you guys have experience with deploying Simulink models out of Vivado System Generator to the ARTY S7 board? Thanks in advance
  2. Pradipta Kumar Pal
    Please confirm if the Basys 3 Artix-7 FPGA Trainer Board is supported by the Vivado System Generator on Simulink®.
  3. QuaternionGang
    I wish to use the Analog Discovery 2 as a power supply for a set up which will involve variable currents through a helmholtz coil configuration in order to model the Upper Atmosphere's Magnetic Field. I will be running a real time model in Simulink that will contain values of the magnetic field in several directions. I have the coils set up so that a known current, and thus voltage, should be able to create the magnetic field in the center, which will be detected by a magnetometer. I would like to send the Simulink values to the Analog discovery to alter the voltage output of the Analog Discovery accordingly so that the current in the coil setup can vary in real time, thus spoofing the magnetic field for the magnetometer. Is this something that is possible with the Analog Discovery 2.
  4. Dimitry

    Vivado filter project

    Dimitry posted a question in FPGA

    Hello, I'm new in FPGA and I'm trying to realize a filter using the FPGA Nexys 4 on Simulink. I have already done the Simulink circuit and export it to the Vivado Design sout as a project. Here I choose the right FPGA but i have problem with I/O Ports planning. My output of this project will be a filter which will realize the filtration of biological signal (ECG) which i will bring on JXAD input port on FPGA. Can somebody please help me with realization in Vivado and tell me, which output can be the best after the filtration? Your help means very much to me...