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Showing results for tags 'signals'.
Hello, As I am a novice to Verilog/SystemVerilog, I am seeking for some guidance regarding writing Verilog logic from purely just a timing diagram. (You may have seen my other posts). For example, if my goal is to implement a logical block that has X inputs and Y outputs for the DUT, and all I am given is a timing diagram that shows the behavior of the input and output signals and how they behave according to the supplied clock. What is the best way to tackle this problem from an engineering perspective? Should I be considering to first simply layout the module with the inputs a
Hello, For a project in one of my courses my adviser asked me to find a way to control the sample rate and record length in the Analog Discovery in order to understand how to use the FFT module. Thank you, cjobi247