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Found 6 results

  1. I'm at a complete loss trying to get the Arty A7-100t onboard DDR-SDRAM to behave reliably. Let me start by telling you what I've done (maybe some of this will be helpful for others): The Arty A7-100t is running totally unmodified (no PMOD, ChipKit, etc.). I've generated a Memory Interface Generator (MIG) IP core as per Digilent's recommendations: Digilent MIG Resources My XCI and PRJ files: ddr_sdram_mig.xci and ddr_sdram_mig.prj I've written a simple DDR SDRAM Interface module, based on the approach found on Numato. Unlike the reference code,
  2. Hello! I have an example design where I am writing values into a BRAM. I have confirmed through simulation that the values are stored correctly. However, what I want to do is to confirm that the values are saved running on hardware as well? I have been trying to debug using the TCF debugger and trying to check the Memory window on the uB but I am not getting anything sufficient or understandable. What should I do if I want to, for example, test my memory through the MicroBlaze, shall the D-cache and I-cache be enabled? Could you giv
  3. Hello! I have been investigating how multiple clock domains work and how you can send data ASAP from a camera module to a SDRAM (taking a pic). I am currently using a Nexys-Video and a Zed board and wonder if I could get some tips. The problems I encountered during my research is: -The picture I take has to be stored ASAP, meaning I have to use the mig7 interface for the SDRAM and HDL code. However this will be hard since it requires me to understand how the MIG7 works and thus writing a HDL that is adjusted to work with it. - What is the maximum f
  4. Hello I need advice on which FPGA board to select for a camera project I'm working on. This is the first time I have considered using an FPGA so my knowledge is limited. Any general advice about first use of FPGAs would also be appreciated. It needs the following main features and capabilities. 1. It needs to be able to interface with the image sensor which uses 1.8v logic. I read somewhere that different voltages can be used for certain sections of some FPGAs which would be very useful in this case. 2. SDRAM as a temporary store for captured images. I see that some boards
  5. UCF/XCF data of of SDRAM on board of Genesys 2 isn't inside the provided XDC file (Pin allocation of SDRAM is missing). Anyway Connectivity can be solved manually recovering pin names and functions from the provided board schematic. Should be better to fill these data inside XDC reference file.
  6. Hi, I am trying to interface ddr2 SDRAM with microblaze using PLB bus. I also used central DMA controller. I have problem of generating UCF file for memory based on Atlys board. Any one can help me? Regards