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  1. I've given up on working with the Arty Z7-20 with 20.1 and reverted to Vivado 19.1 and the 19.1 SoCSDK. Using petalinux tools and Petalinux-Arty-Z7-20 project I've been able to create a bootable Linux SD image. So far so good! My objective is to port a project adding AXI slave IP, Linux drivers and applications. The aforementioned project contains a Petalinux-Arty-Z7-20-2017.4-1.bsp file which in turn contains the projects matching Arty_Z7_20_wrapper.bit IP. This project seems like a good starting point for what I need, but where can I find the correct project used to generate Arty_Z7_20_wr
  2. Hello folks, I am working on zynq 7000 board in which artix 7 fpga is there.In the old design spartan 3 was used. I am working on migration from ISE 8.1 to vivado 19.1. I have migrated vhdl code easily but facing problem in migration of processor side. I have created a new block design in vivado by using IP integrater with the reference of MHS file in ISE. In ISE 8.1 block design program run from SPI FLASH which is connected to microblaze and which copy the contents from FLASH to SRAM (external memory connected to microblaze in block design). In zynq 7000 as FLASH