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Found 5 results

  1. I'm trying to build a design for the Arty A7-100 (not using MicroBlaze), using the AXI Quad SPI memory for user data (and also for bitstream storage). The Reference Manual (and the master .xdc file) mention six external pins for this (actually the .xdc file only mentions five). But when I select the Arty A7100/External Memory/Quad SPI Flash from the "Board" window, it gives me a block for which the SPI_0 interface has 18 pins. Essentially each data pin has become three (_i, _o and _t). Am I supposed to put IO buffers there myself, or have I somehow got the wrong block? If so, please would
  2. dfdias

    AXIQUADSPI-ACL-NEXYS4

    Hi was trying to interface the accelerometer available on the nexys 4 board. But i was not getting any data. Then I mapped the output pins to the JA PMOD header so I could probe them Using an logic analyzer I saw that the sclk and Chip_select were working but the MOSI signal is full of zeroes. I connected an 50MHz clk coming from the clock wizard, and then connected it to the ext_spi_clk and used an scale of 16 so the clk is about 3.16MHz Below is the Block_Design helloworld.c Below is the data I acquired using saleae logic analyzer:
  3. I'm stumped and have been pouring through the posts in these forums over the last couple of days but can't quite get to a solution. I know this has sort of been beaten to death...so take it easy on me. I'm trying to get the Arty A7-100T board to boot from SPI flash on power-up. I'll try to go in the order of which I've configured things as concisely as possible...any insight or help is much appreciated. IP block in Vivado is customized as shown in image below. In addition, I've connected 'ext_spi_clk' to a 50MHz clock generated by the clocking wizard. Bitstream generates succes
  4. Hi all, I'm confused about storing bitstream into the SPI memory that is on board and how to use a SPI bus to interface external peripheral. To be more specific if I need to use the on board SPI memory (IC3 on the schematic board) to store my bitstream I've to add the AXI Quad SPI attached to my Microblaze or this memory is adreessed automatically from the FPGA at startup? If instead only use the on board SPI memory to store my bitstream and then autoconfig the FPGA on startup I need to drive external SPI peripheral (e.g. and DAC) I've to add the AXI Quad SPI and then drive it f
  5. Hello, I'm having some issues with multiple (16bit) transactions while holding slave select low. I'm using the example master polling spi code from the xilinx SDK, and have manual slave select working where it holds the SS line low while performing the multiple transactions, and once finish it goes high again. My issue is that i'm trying to make a simple slave which can write to a register continuously if it receives a write command from the master, and then if a read command is sent from the master, the slave will send back whatever is in the designated register requested by the master.