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Found 18 results

  1. Hi, I am working on a project where i'm using Digilent zybo AP SoC with xilinx vivado for Hardware design and Xilinx SDK for software design. My application uses following protocol/peripherals: 1. UARTns16550 PL side (Programmable Logic) in interrupt mode. 2. GPIOs 3. Ethernet mac (lwIP stack) I started my software design using xilinx lwip perf client application project. Then i started modifying the perf client C code according to my need. My project contains Uartns16550, tcp/ip server and client program which receives real-time data. So coming to my problem, i am able to run my application from xilinx sdk GDB and system debugger. But, when i dump my code in QSPI flash and try to boot, the zybo is not booting up. I also tried loading different application project like tcp perf server, perf client. By doing this the processor boots up properly through QSPI flash. I followed the steps provided by Digilent for programming the flash and i also ensured that the jumpers are in the right place where it has to be. I believe that there's a problem with my program since i have started modifying the tcp perf client code for my project. I am not getting a clue where my code is going wrong. Operating System : Windows 10 Software : Xilinx vivado 2018.3/SDK 2018.3 Any inputs related to this will be appreciated. Thanks & Regards Ajeeth kumar
  2. Is it possible to write a VERILOG / VHDL code to download the programming file (fpga bitstream) to the hardware device (for example an SPI flash memory)? I'm asking this, because I would like to transfer a bit stream into a spi flash memory, which will then be mounted on an fpga card for boot and configuration. I have already written a few lines of code to write, read, and erase the contents of the 32 MB NOR flash memory (PMODSF3). I tested my code and it works without problems! However, how to read the bitstream, before writing it to the flash memory? Do I only need to transfer the bitstream into flash memory or do I have to add a header and a footer in the memory before and after the transfer of the bitstream file? Have you ever worked on a similar project? N.B: I am using a Xilinx FPGA (Artix-7) on a customized board. I would like to find an alternative solution to the Xilinx hardware manager to program the SPI flash. Any ideas, feedbacks and suggestions are welcomed! Thank you Hervé
  3. Hello all, some months ago I had a Basys 2 Board that I perfectly could program via multisim, designing an schematic and then exporting the design. Now I have an Arty S7 on my hands and I would wish to do the same. I followed the tutorials: http://www.ni.com/tutorial/14871/en/ and https://reference.digilentinc.com/learn/programmable-logic/tutorials/program_fpgas_through_multisim/start An instance for the Arty S7 was created in multisim and it gave me the option to generate the VHDL file from the design (I haven't verified the file yet). Multisim won't give me the programming option. I checked the configuration files for others working boards and there is a missing line for programming, like Device ID etc. Mi question, does anybody has tested programming the arty s7 from multisim? if not is it possible? directions ? Best Regards, Edwin Marte
  4. I am interested in buying Spartan-7 FPGA Module: https://store.digilentinc.com/cmod-s7-breadboardable-spartan-7-fpga-module/ but first I would like to know if it suffers same USB cable issue as CMOD-A7: Since FTDI circuitries look similar on these two boards I just want to make sure the faulty design was not copied over from A7 onto S7.
  5. Hello, I'm planning on buying the product "Cmod C2: Breadboardable CoolRunner-II CPLD Module" to make some prototypes of future designs. I saw that, in order to program its CPLD (XC2C64A), I need to buy a USB to JTAG cable. Is the Diligent's JTAG-HS1 programming cable compatible with that CPLD and board?. I will be using the last version of ISE on Windows 10, will it be a problem?. If it helps answering, this are the links of the Digilent's store of those products: Breadboardable CoolRunner-II: https://store.digilentinc.com/cmod-c2-breadboardable-coolrunner-ii-cpld-module/ JTAG-HS1 programming cable: https://store.digilentinc.com/jtag-hs1-programming-cable-limited-time/
  6. Caleb

    Im completely new to this

    Hi, I'm just getting into programming FPGAs and I've made my first program "blinky light" but I cant get my computer to either find the FPGA when connected or I'm missing a step when I set up Vivado. I've ran the Synthesis, Implementation, and generated the bitstream and everything completed without any errors. I just need to know how to do last part which is to put the code on the FPGA. Thanks! What I'm using/running: Ubuntu 18.04 (OS on my computer), Vidado WebPack, Arty A7 35t, and if it helps I programmed it in Verilog
  7. Does Digilent offer any services for custom script programming to control the Analogue Discovery 2? I need to better harness the device's existing capabilities in a more streamlined manner and it would be much easier to contract this work to an expert instead going through the scripting process myself.
  8. I have a Wi-FIRE rev C board that I would like to program from the Arduino IDE. According to the ChipKIT wiki, the ChipKIT core has replaced the need for MPIDE. I hooked up the Wi-FIRE to the UART mini-USB on the top of the board (Call out 26 in the ref manual) and then tried to program from the Arduino IDE by selecting "Sketch > Upload" but I get an the following error Programmer for Microchip PIC32 microcontrollers, Version 2.1.24 No target found. Copyright: (C) 2011-2015 Serge Vakulenko An error occurred while uploading the sketch My guess is that I need to use my chipKIT PGM programmer, but the Wi-FIRE ref manual does not discuss how to connect this. For example, JP3 and JP4 are not mentioned in the manual at all. (They are two, six pin staggered holes, one of which is labeled "JTAG"). It doesn't help that the PGM doesn't have much room to make a connection with all of the other stuff on the top of the board. Am I missing something obvious? UPDATE: I needed to change the selected COM port under "Tools" in the Arduino IDE. (Stumbled across Figure 9 here https://learn.digilentinc.com/Module/103?position=0
  9. All: I've been incrementally developing both hardware (MicroBlaze with AXI peripherals) and software for the MicroBlaze itself. I've set up my software program size so that all software and hardware configuration can fit into a single .bit file. I've been able to program the flash several times, but yesterday have been getting errors while attempting to erase the flash. Notes are below. Is there a HW/SW program I could load onto the FPGA to prove or disprove that the flash is broken? Thanks!! Peter From the Vivado side: create_hw_cfgmem -hw_device [lindex [get_hw_devices] 0] -mem_dev [lindex [get_cfgmem_parts {n25q32-3.3v-spi-x1_x2_x4}] 0] set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] set_property PROGRAM.FILES [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0]] set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] set_property PROGRAM.CHECKSUM 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] startgroup if {![string equal [get_property PROGRAM.HW_CFGMEM_TYPE [lindex [get_hw_devices] 0]] [get_property MEM_TYPE [get_property CFGMEM_PART [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]]]] } { create_hw_bitstream -hw_device [lindex [get_hw_devices] 0] [get_property PROGRAM.HW_CFGMEM_BITFILE [ lindex [get_hw_devices] 0]]; program_hw_devices [lindex [get_hw_devices] 0]; }; INFO: [Labtools 27-3164] End of startup status: HIGH program_hw_cfgmem -hw_cfgmem [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] Mfg ID : 20 Memory Type : ba Memory Capacity : 16 Device ID 1 : 0 Device ID 2 : 0 Performing Erase Operation... Erase Operation failed. ERROR: [Labtools 27-3161] Flash Programming Unsuccessful ERROR: [Common 17-39] 'program_hw_cfgmem' failed due to earlier errors. From the XSDK side: bootgen -arch fpga -image \ /home/pmeyer/WORK/DA-Test/ChameleonFPGA/UARTSlaveController/UARTSlaveController.sdk/top_hw_platform_0/cache/bootimage.bif \ -w -o \ /home/pmeyer/WORK/DA-Test/ChameleonFPGA/UARTSlaveController/UARTSlaveController.sdk/top_hw_platform_0/cache/BOOT.bin \ -interface spi program_flash -f \ /home/pmeyer/WORK/DA-Test/ChameleonFPGA/UARTSlaveController/UARTSlaveController.sdk/top_hw_platform_0/cache/BOOT.bin \ -offset 0x00000000 -flash_type n25q32-3.3v-spi-x1_x2_x4 -blank_check -verify -cable type \ xilinx_tcf url TCP:127.0.0.1:3121 ****** Xilinx Program Flash ****** Program Flash v2016.3 (64-bit) **** SW Build 1682563 on Mon Oct 10 19:07:26 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. Connecting to hw_server @ TCP:127.0.0.1:3121 Connected to hw_server @ TCP:127.0.0.1:3121 Available targets and devices: Target 0 : jsn-Cmod A7 - 35T-210328A2B5A8A Device 0: jsn-Cmod A7 - 35T-210328A2B5A8A-0362d093-0 Retrieving Flash info... Initialization done, programming the memory Performing Erase Operation... Erase Operation failed. ERROR: Flash Operation Failed Server disconnected during TCF command /home/pmeyer/3rdParty/SDK/2016.3/bin/loader: line 164: 20344 Segmentation faul
  10. Hi there, I've just started with CPLD design, using the Digilent Coolrunner II CPLD starter board (Rev. 3.0) and successfully synthesized my code with the Xilinx ISE development software. I would now like to integrate a Cmod breadboardable CPLD module into one of my projects. I don't own a programming cable/adapter, so I was wondering if I could use the Starter Board as a programmer via its JTAG interface. Looking at the schematic, I could not find a way to connect a JTAG daisy chain with another external CPLD, because the JTAG signals are all connected in parallel. Would it be possible to simply not power the CPLD on the Starter Board (detatching JP2) and connect the external CPLD to the JTAG pins? Best regards Stefan
  11. Hi, I have just received a CMOS S6 evaluation board (410-282P-KIT). Before I program it with my development code I wanted to verify my setup is working Ok. I am using Xilinx 14.7 on a Windows 7 PC. I have loaded iMPACT and successfully initialised the scan chain. I assigned the demo bit file to the FPGA and the demo mcs file to the flash device. When I ask it to iMPACT to verify the contents of the flash memory it fails at address 0. The iMPACT console output is displayed below. INFO:iMPACT - Current time: 11/07/2016 13:18:16 PROGRESS_START - Starting Operation. Maximum TCK operating frequency for this device chain: 25000000. Validating chain... Boundary-scan chain validated successfully. '1': IDCODE is '012018' (in hex). '1': ID Check passed. '1': IDCODE is '012018' (in hex). '1': ID Check passed. '1': Reading device contents... Failed at address, 0 '1': Verification Terminated PROGRESS_END - End Operation. Elapsed time = 1 sec. Is it possible to verify the PROM contents and if so what am I doing wrong? Regards, Stewart.
  12. I'm very confused as to why I can't get 3 GPIO's to work as desired. I'm trying to program 3 external shift registers. The control lines are Clk, Latch, Output Enable and Data In. I've implemented a ~240Hz timer to cycle between 4 16-bit values to be sent to the shift registers. Everything works except the 3 data inputs. The actual failure is the bit shifting and mask of each of the 16-bits of the 3 data in variables. I'm including my code and an analyzer trace (uc32 pins directly to a Saleae logic analyzer). I'd appreciate anyone that could shed some light. Thanks! Test.pde /* To turn on any given channel, set the pin LOW. To turn off, set the pin HIGH. The higher the analogWrite level, the lower the brightness. This example code is in the public domain. */ #define __32MX340F512H__ 1 #include <p32xxxx.h> #include <plib.h> #define CLK 0x0400 // D10 #define Ou1 0x0080 // D07 #define Ou2 0x0040 // D06 #define Ou3 0x0020 // D05 #define OE 0x0010 // D04 #define LE 0x0008 // D03 #define E0 0x0040 // G06 #define E1 0x0080 // G07 #define E2 0x0100 // G08 #define E3 0x0040 // F06 #define INDCTR 0x0800 // D11 #define CTR1 0x0020 // F5 #define CTR0 0x0010 // F4 #define PIN_CLK 8 #define PIN_Ou1 37 #define PIN_Ou2 36 #define PIN_Ou3 34 #define PIN_OE 10 #define PIN_LE 9 #define PIN_E0 13 #define PIN_E1 12 #define PIN_E2 11 #define PIN_E3 38 #define PIN_CTR1 40 #define PIN_CTR0 39 #define PIN_INDCTR 35 #define CPU_HZ 80000000 #define TICKS_PER_SECOND (CPU_HZ / 2) #define Tx_ON 0x8000 #define Tx_PS_1_8 (3 << 4) #define Tx_SOURCE_INT 0 volatile uint32_t counter = 0; volatile uint32_t intHit = 0; volatile uint32_t eCount = 0; volatile uint32_t OutA1[4] = { 0xaaaa, 0x5555, 0x9999, 0x6666 }; volatile uint32_t OutA2[4] = { 0x5555, 0x9999, 0x6666, 0xaaaa }; volatile uint32_t OutA3[4] = { 0x9999, 0x6666, 0xaaaa, 0x5555 }; /* Define the Interrupt Service Routine (ISR) */ void __attribute__((interrupt)) myISR() { ++counter; if ( counter == 4 ) counter = 0; intHit = 1; if ( counter & 0x01 ) LATFSET = CTR0; else LATFCLR = CTR0; if ( counter & 0x02 ) LATFSET = CTR1; else LATFCLR = CTR1; LATDSET = INDCTR; _nop(); LATDCLR = INDCTR; clearIntFlag(_TIMER_3_IRQ); } /* start_timer_3 */ void start_timer_3( uint32_t frequency ) { uint32_t period; period = TICKS_PER_SECOND / frequency; T3CONCLR = Tx_ON; /* Turn the timer off */ T3CON = Tx_PS_1_8; /* Set the prescaler */ TMR3 = 0; /* Clear the counter */ PR3 = period; /* Set the period */ T3CONSET = Tx_ON; /* Turn the timer on */ } void setup() { // Initialize serial communications: Serial.begin(115200); Serial.println("hello"); // Set all used outputs to open-drain ODCDSET = CLK | Ou1 | Ou2 | Ou3 | OE | LE | INDCTR; ODCFSET = E3 | CTR1 | CTR0; ODCGSET = E0 | E1 | E2; // Set all used outputs to a low LATDCLR = CLK | Ou1 | Ou2 | Ou3 | OE | LE | INDCTR; LATFCLR = E3 | CTR1 | CTR0; LATGCLR = E0 | E1 | E2; // Set all Analogue pins to digitial AD1PCFG = 0xffff; // Set LED Control outputs to normal TTL, not open-drain ODCDCLR = CLK | Ou1 | Ou2 | Ou3 | OE | LE | INDCTR; ODCFCLR = E3 | CTR1 | CTR0; ODCGCLR = E0 | E1 | E2; // set LED control pins as outputs TRISDCLR = CLK | Ou1 | Ou2 | Ou3 | OE | LE | INDCTR; TRISFCLR = E3 | CTR1 | CTR0; TRISGCLR = E0 | E1 | E2; // Disable the interrupt-on-change for IO pins CNCONCLR = 0xe000; // Set OE to high LATDSET = OE; counter = 8; intHit = 0; start_timer_3( 60 * 4 ); /* 240 Hz */ setIntVector( _TIMER_3_VECTOR, myISR ); setIntPriority( _TIMER_3_VECTOR, 4, 0 ); clearIntFlag( _TIMER_3_IRQ ); setIntEnable( _TIMER_3_IRQ ); } void loop() { int i, j; int to1, to2, to3; if ( intHit ) { eCount = counter & 0x03; /* Make sure CLK and LE are low */ digitalWrite( PIN_CLK, LOW ); digitalWrite( PIN_LE, LOW ); /* Make sure OE is hi */ digitalWrite( PIN_OE, HIGH ); /* Prepare the Out Data lines by setting them LOW */ digitalWrite( PIN_Ou1, LOW ); digitalWrite( PIN_Ou2, LOW ); digitalWrite( PIN_Ou3, LOW ); to1 = OutA1[eCount]; to2 = OutA2[eCount]; to3 = OutA3[eCount]; for ( i = 0; i < 16; i++ ) { /* Test Red */ if ( to1 & 0x01 ) { digitalWrite( PIN_Ou1, HIGH ); } /* Test Green */ if ( to2 & 0x01 ) { digitalWrite( PIN_Ou2, HIGH ); } /* Test Blue */ if ( to3 & 0x01 ) { digitalWrite( PIN_Ou3, HIGH ); } /* Toggle CLK */ digitalWrite( PIN_CLK, HIGH ); digitalWrite( PIN_CLK, LOW ); to1 = to1 >> 1; to2 = to2 >> 1; to3 = to3 >> 1; } /* Toggle LE, then set OE low */ digitalWrite( PIN_LE, HIGH ); digitalWrite( PIN_LE, LOW ); digitalWrite( PIN_OE, LOW ); digitalWrite( PIN_E0, LOW ); digitalWrite( PIN_E1, LOW ); digitalWrite( PIN_E2, LOW ); digitalWrite( PIN_E3, LOW ); switch ( eCount ) { case 0: digitalWrite( PIN_E0, HIGH ); break; case 1: digitalWrite( PIN_E1, HIGH ); break; case 2: digitalWrite( PIN_E2, HIGH ); break; case 3: digitalWrite( PIN_E3, HIGH ); break; default: break; } intHit = 0; } }
  13. When I updated the FTDI VCP drivers(http://www.ftdichip.com/Drivers/VCP.htm ,win7 X64 2.12.10), the ARTY onboard JTAG disappeared. And there are two USB-TO-COM on my computer. See attachment, please. Any suggestions? JTAG.not.work.rar
  14. Hello All, Just joined the forum, I just received my Arty board, and ported a very simple 32 bit counter design that drives LEDs (slower bits). I can synthesize and implement the design (no warnings), I can view the schematic and it looks exactly like the RTL, however, when I try to load it onto the target I get the following warning: WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. The board does nothing! I use this exact same code on another FPGA board (Altera Cyclone-5) and it works fine... I'm assuming that the above warning is critical because after the download the boards doesn't do anything Thanks for any help! -Paul
  15. Hello, I would like to program ARTY board with an open source programmer (like openocd or xc3sprog). Did someone managed to program the board (either load a bitstream to FPGA or write to Flash) with an open source programmer? I tried to add the IDCODE / IR-len to devlist.txt in xc3sprog and recompile but here is what I get: yann@pcqu1r0x:~/dev/xc3sprog$ cat devlist.txt | grep XC7A35T 0362D093 6 0x09 XC7A35T yann@pcqu1r0x:~/dev/xc3sprog$ ./xc3sprog -c ftdi -v -j XC3SPROG (c) 2004-2011 xc3sprog project $Rev: 774 $ OS: Linux Free software: If you contribute nothing, expect nothing! Feedback on success/failure/enhancement requests: http://sourceforge.net/mail/?group_id=170565 Check Sourceforge for updates: http://sourceforge.net/projects/xc3sprog/develop Using devlist.txt Using cablelist.txt Cable ftdi type ftdi VID 0x0403 PID 0x6010 dbus data 00 enable 0b cbus data 00 data 00 Using Libftdi, Using JTAG frequency 1.500 MHz from undivided clock No JTAG Chain found USB transactions: Write 5 read 2 retries 0 Any idea? Looks like the board is using the usual FTD2232 chip so I thought just using the -c ftdi cable would work... I tried others from the cablelist.txt without success... Thanks!
  16. Hello, I have successfully programmed my Basys2 using the 'djtgcfg' utility under Linux dozens of times, but I'm no longer able to do so. When I attempted to program the board yesterday, I got some unusual results: > djtgcfg enum Device: 3.....O......<. Product Name: Digilent Basys2-100 User Name: 3.....O......<. Serial Number: 210155528315 > djtgcfg init -d 'Basys2' ERROR: unable to open device "Basys2" > djtgcfg init -d '3.....O......<.' ERROR: unable to open device "3.....O......<." *I used the '.' character in the strings above to represent non-printable characters, because the replacement character used by my terminal won't display properly on this page. Using the product name or serial number yields a similar result. It appears that I can't communicate with the device due to a corrupted device ID. However, my computer has no trouble recognizing the Basys2 board: > lsusb ... Bus 003 Device 011: ID 1443:0007 Digilent Development board JTAG ...For what it's worth, here is the hexdump of the djtgcfg result above: > djtgcfg enum | xxd 0000000: 466f 756e 6420 3120 6465 7669 6365 2873 Found 1 device(s 0000010: 290a 0a44 6576 6963 653a 2033 fbbb b0df )..Device: 3.... 0000020: e04f a81f bdff bbf9 ec3c ad0a 2020 2020 .O.......<.. 0000030: 5072 6f64 7563 7420 4e61 6d65 3a20 2020 Product Name: 0000040: 4469 6769 6c65 6e74 2042 6173 7973 322d Digilent Basys2- 0000050: 3130 300a 2020 2020 5573 6572 204e 616d 100. User Nam 0000060: 653a 2020 2020 2020 33fb bbb0 dfe0 4fa8 e: 3.....O. 0000070: 1fbd ffbb f9ec 3cad 0a20 2020 2053 6572 ......<.. Ser 0000080: 6961 6c20 4e75 6d62 6572 3a20 2032 3130 ial Number: 210 0000090: 3135 3535 3238 3331 350a 155528315.So it appears the device ID as seen by djtgcfg is 33fb bbb0 dfe0 4fa8 1fbd ffbb f9ec 3cad 0aA couple of other details that might be helpful: I succesfully programmed a friend's Basys2 multiple times using djtgcfg after having this problem with my board. When using his board, the output from djtgcfg was normal (all printable characters).After experiencing this problem under Linux, I sucessfully programmed my Basys2 from a Windows machine. When using Adept2 under Windows, the device ID string still appears corrupted, but I am able to program it anyways. I don't have regular access to a Windows machine, so I'd really like to get this working under Linux again. I'm hoping this is just an issue of some corrupted Flash or EEPROM in the AT90USB that could be fixed by reprogramming it... but I'm not sure what to try next. Any ideas? Thanks for reading!
  17. Hello guys, I have a problem to configure the digital output of my Analog Discovery with a custom designed/programmed signal. I can handle the fundtions given in Waveforms and watched the tutorials. The plan is to generate a PWM with the device in C++. As compiler I am using CodeBlocks. I tried to generate a sine, which is given in the samples of waveforms, but right there I am stuck. I included the samples.h and managed, that the dwf.h is included. In Waveforms itself I only can import .txt files. Because of that I think I have to connect with the Analog Discovery with the commands out of the "WaveForms SDK Reference Manual". After building the sample sine signal, my compiler gives me the error, that something in the dwf.h is noch correct. The compiler is confused by the expression "DWFAPI" in every line in dwf.h. The error message is: "expected identifier or '(' before string constant". I could not find a tutorial fiiting my problem, so I hope to find some answers or solutions right here Thanks for help!
  18. Hi everybody, I have just bought a Genesys Board (Virtex 5 FPGA) and I want to use the Xilinx iMPACT Tool to program it through the dedicated USB port. Is there any documentation available about step-by-step configuration and programming of the Genesys with the iMPACT Tool, for beginners? Thank you! Holly87