Search the Community
Showing results for tags 'pll'.
I need to use the IBERT IP core on a Genesys-2 FPGA board. I am using FMC-SMA board to convert FMC into SMA. In the clock settings I am using the external clock source from pin AD-11/12 of 200MHz. But the problem is I am unable to get any output as PLLs are not locked. I had followed the same steps with FMC board and all things where working fine. 1. Can I use the internal clock in the clock setting. (I tried but getting the INFO:- [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. ) 2. Do I n
Hello everyone, I am facing a problem create an instant of the PLL I setup from the Clocking Wizard. My goal is to provide my PWM module a much faster clock than the 100MHz one. I am extremely new on verilog programming (I know nothing of this stuff yet lol). My current code throw my 16 errors code that I know absolutely nothing about. Any helps on this would be greatly appreciate. Thank you reading P/s: The below text is my top module. module top( input CLK, input fastClk, output pwm_out1, output pwm_out2, output pwm_out3, wire rst,
Hello to all, I'm facing really strange problems with Arty7 Artix board. In some cases when I generate .bit file for my microblaze design, there is no locked signal from the clocking wizard. Please check attached image. Input of clocking wizard is directly connected to E3 pin and "locked" signal is connected to the one of the board's LEDs. The rest of my design is composed of MicroBlaze instance with Ethernet IP core, MIG, UART, SPI flash core and "glue" logic for these components. I'm using Vivado 2017.2 or 2018.1, win 10 x64, win 7 x64, no matter. Input clock is present, I h
Hi everyone, I'm sure that someone has used a PLL in an Arty design....I have tried and keep getting an implementation error as follows: [DRC 23-20] Rule violation (REQP-1712) Input clock driver - Unsupported PLLE2_ADV connectivity. The signal xilinx_ip_pll/inst/clk_in1 on the xilinx_ip_pll/inst/plle2_adv_inst/CLKIN1 pin of xilinx_ip_pll/inst/plle2_adv_inst with COMPENSATION mode ZHOLD must be driven by a clock capable IO. The Arty Clock100 comes in on Pin E3, so I'm assuming that this is a clock capable input..? (can't be moved...) I even tried instantiating a BUFH in the top level before the