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Found 6 results

  1. Esti.A

    OpenCV and Pcam5-c

    Hi everyone, I am working in teh demo that was created by Digilent to get images from teh Pcam5-c that is connected by a MIPI CSI-2 interface to teh zybo z7-020 board. In this case, I was wondering if I decide to do the processing of the image (edge detection, enhancement of light,...) I would need to use SDx. I have seen that there are plenty of solutions in OpenCv but I dont know how the hardware proyect and the SDx project can be linked. Note, in this initial design I have teh initiallization od teh camara and platform in a C++ application file that I dont know how if I should export to sdx file and how does this interact with the platform. Anothr queation I have is that for interacting with the openCv set-up do I must use Linux ? Kind regards Esti
  2. Hello, I have a Arty-Z7-20 board and got the hdmi_in demo working on it. I need to process the incoming hdmi stream and I found that doing it as an application on Zynq is too slow because pixel accesses are required. I would like to use the OpenCV functions in HLS to do this. I wrote the following program in HLS - #include <hls_video.h> void video_resize(hls::stream< ap_axiu<24,1,1,1> > &video_in, hls::stream< ap_axiu<24,1,1,1> > &video_out) { #pragma HLS INTERFACE axis port=video_in bundle=INPUT_STREAM #pragma HLS INTERFACE axis port=video_out bundle=OUTPUT_STREAM hls::Mat<1080, 1920, HLS_8UC3> src; hls::Mat<1080, 1920, HLS_8UC3> dst; #pragma HLS dataflow hls::AXIvideo2Mat(video_in, src); hls::Scale(src, dst, 2.0, 0.0); //Simple processing hls::Mat2AXIvideo(dst, video_out); } My questions are - 1) Where in the demo block design should I connect this? (a) Between the video-to-axi4-stream ip and the axi-vdma ip (b) Add 1 more axi-vdma IP with both read and write channels and connect to it (c) Some better alternative? 2) In HLS, this design was synthesized with a clock constraint of 6.7 ns, so it meets the HDMI clock constraint of 148.5 MHz. However, in IP Integrator, a default value of 100 MHz is taken and I am unable to change this. What is the solution? 3) Is there any Digilent reference design/demo that already has HLS OpenCV IP integrated into the block design? Xilinx provides XAPP1167, but this only compiles on 2014.4 version which I don't have. I don't know how to upgrade the design to the current version. I might be asking too much, but any help is appreciated. Thanks, Rajat Rao
  3. Hi everyone, I'm running Xillinux on my Zybo and I want to do some projects with opencv but I can't fin how can I download it, can anyone help me?? Thanks!
  4. Hi every one, I want to a IP CORE for face detection that created by HLS. According to OpenCV function for face detection (Cascade Classifier), I found similar function in “hls/hls_video_haar.h” in to “hls_video.h” library, But I don’t know How can I use these function for face detection. Please help me about these topic. Best wishes.
  5. Hello all tech-lovers; Do any of you guys have experience using Eigen library (http://eigen.tuxfamily.org/index.php?title=Main_Page) in bared metal OS ? When I try to define a matrix like : xil_printf(" TP CC 0 \r\n "); MatrixXd m1(6,6); MatrixXd m1_inv(6,6); xil_printf(" TP CC 1 \r\n "); the program is compiled and built, but when running it on the board, it HALT happens! I saw the assembly code of the line that exception happens, it is 0010da80: ldr r0, [r0] in which r0= 3758100524 I think the halt is because of referring to the address( decimal: 3758100524, Hex: E000102C )which is out of range of the address bus of Zybo! However this code works fine on PC ( X86) But I don’t know why my c codes convert to this assembly code. I would appreciate if any of you guys have any hint or experience on that.
  6. One Query Zybo board which has znyq 7000 chip. Does it have the capability to support Open cv applications like zed board ??