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Found 56 results

  1. Hi. I have implemented the Nexys Video looper demo, according to the manual, following all the steps. Unfortunately, after implement and configure the FPGA, using Vivado, the demo did not work properly, the LCD works perfectly, also the control buttons, but the sound did not appear in line out, with the headphone connected. If someone knows especial details in order to use line in and line out, different to the especified in the guide, please let me know, also if someone have implemented this demo succesfully. Thanks in advance.
  2. This question was posted on YouTube: Does the Nexys Video have the ability to ingest/output [email protected]? Thank you, Digilent Studio
  3. The HDMI2USB project aims develops affordable open hardware options to record and stream HD videos (from HDMI & DisplayPort sources) for conferences, meetings and user groups. Our current focus is on around custom gateware running on FPGA hardware, our gateware if fully open and can be found on github. The gateware allows for both full matrix functionality and capture via either USB or Ethernet. A control terminal is also available giving the computer complete management of all functionality. We have been using the Digilent Atlys as a prototyping platform and are investigating also supporting the Digilent Nexys Video. We are also developing our own hardware the Numato Opsis. As an open source project, we'd love help continuing to develop new features and functionality. We are actively seeking assistance: For video recording individuals+teams: Be an early adopter; get a board, start using it, report back to us with feedbackFor software/FPGA developers: Get involved in contributing code both to the capture software + FPGA stackOur aim is this becomes the defacto, incredibly affordable and easy to use video recording hardware for conferences, meetings and user groups worldwide. Find out more about HDMI2USB and why we’re doing this in ABOUT + FAQ
  4. Hi, I am new to this Digilent Forum and have questions to ask. I plan to use both HDMI sink and HDMI source at the same time for my current project. The HDMI input will connect to HD camcorder and the incoming video streams will be processed by FPGA and displayed onto either a monitor or TV through HDMI output. I read somewhere that both HDMI sink and source can only be used in bypass mode in Nexys Video FPGA board. I have 3 questions to ask 1. Can Nexys Video FPGA board be used for my project? 2. Is it enough use the Vivado free WebPACK license (in terms of IPs) for my project because the Design Edition licenses for Vivado are not yet available for purchase? 3. Do I have any other cheaper choices such as the ZYBO FPGA board? But, the ZYBO FPGA board cannot use the HDMI source and HDMI sink at the same time. Please give me your advice. Thanks, Jim Soong
  5. Hello, The older Atlys boards had a Spartan-6 FPGA which meant the highest progressive resolution supported by the HDMI input and output was 720p (which was always frustrating). I was wondering if that had changed with the newer Series 7 devices like the Zybo or Nexys Video boards? I noticed that hamster was able to get 1080i working. Are SERDES even able to do 1080p theoretically? Thanks for your help! Tim 'mithro' Ansell
  6. I've got my new fractal viewer up and running on the new Nexys Video board. I'm just about to upload the source and a .bit file to http://hamsterworks.co.nz/mediawiki/index.php/Mandelbrot_NG_1080i It does not use any frame buffer - each pixel is completely recalculated every time it is displayed, allowing for super-smooth zooms and pans. Some highlights - Generates video DVI-D at 1080i. It is pretty hard to find examples of how to do 1080i properly. - Outputting over DVI-D, Although it can support 24-bit colour, however for the moment I am just using 64 different ones, as it aids debugging. - Does not use any IP except an unsigned 17x17 multiplier (because it wouldn't infer properly) - Each pixel spends 2,106 cycles going through the calculation pipeline before being sent to the display, - Uses 'only' 540 DSP blocks because when I used more it caused the board to reset itself, so the chip is capable of about 30% more math. - The heatsink gets a little warm... - Currently processes down to iteration 162. I'ld like it to go higher but must solve why it is resetting itself - You have the option of moving some of the DSP multipliers into LUTs, which allows you to calculate 'deeper' at the expense of power usage. - Performs about 120 billion 36-bit operations per second I've also got a 720p version, and a 640x480 that calculates three times as 'deep' per pixel, but that doesn't have the magical 1920x1080 resolution.