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Found 56 results

  1. I used Nexys Video Board for image processing via HDMI Interface. And now i need to make small this board. For this work, I drew the schematic based on the Nexys Video Board's schematic. But i'm a beginner in this field, so i couldn't find exact information to some element. Those elements are this: 1. What does Foot and SHIELD in schematic Sheet 1 means? 2. Some pins could not find the pin connected together Those pins are this: - HDMI_RX_PEEN in Sheet 6 - PROG_ pins on BANK 14 in Sheet 10 (PROG_RDN, PROG_WRN, PROG_D0/SCK, PROG_CLKO, PROG_TXEN, PROG_D3/SS, PROG_D1,MOSI, PROG_SPIEN, PROG_D6, PROG_RXEN, PROG_SIWUN, PROG_D2/MISO, PROG_D7, PROG_D5, PROG_D4) - T3 pin on BANK 34 in Sheet 11 3. There are elements that can't know exact name. - HDMI connect in Sheet 5. (There is comment written HDMI-47151 but i found similar devices: 47151-0001, 47151-1001 etc.) - All of Registers, Capacitors, Ferrite Beads, Jumpers, Switches and LEDs. Because I don't have experience about pcb design, I can't find exact element so i want to see BoM of Nexys Video Board
  2. hello, The following is my description of the problem: I use the FPGA board is nexy Nexys Video A7 board, want to achieve usb and PC information transmission, want to use the synchronization fifo mode,I used FTDI software (FT_Prog.exe) to eeprom into 245fifo mode, but vivado since then show the link is not the device, bit file can not be written. I have two the same board, another board did not eeprom configuration before, vivado can link to the equipment, but after the configuration also appeared in this issue, is not my configuration eeprom there is a problem?Here's my screenshot of the problem。 I hope you will solve this problem for me。 wang
  3. The "Nexys Video™ FPGA Board Reference Manual" (Revised May 30, 2017) describes in Table 9 (page 20) the "Recommended usage" of the pins of JXADC with "LVDS_25 input/output" (with V_ADJ=2.5V). However, the discussion in has led to the result that LVDS-standard is not supported without changing the board. I would recommend to change the reference manual at this point. The documentation should clearly name supported standards especially if it is targeted to students that may not know all details of the IO-standards. The best way of a replacement of "LVDS" would be a list of IO-standards that work on this connector without changing the board. If the list is too long (the list of standards supported by Artix-7 fills several pages) it can be moved to the appendix. The minimal solution would be the replacement of "LVDS" by "differential" and let to the user/student to find out if a certain standard can be implemented with the board. Btw. There is a small typo in the table: The 3rd differential pair of JXADC is 3-9 (according to the schematic).
  4. Hello! I use Nexys Video board and plan to use a Pmod connector with LVDS standard (input and output). Following the reference manual, the only Pmod connector that provides LVDS (LVDS_25) for input and outputs is JXADC (with V_ADJ=2.5V). This connector is equipped with 100 ohm series resistors. The Xilinx documentation UG471 (v1.8, pages 91-93) does not describe that series resistors are recommended or required. Is it possible to use Pmod connector JXADC for LVDS inputs and outputs with that board? Or must I short cut the series resistors (R42-R45/R47-R50)? Many thanks in advance!
  5. Hello all! I'm trying to do some work with a Nexys Video board, and came across an error regarding the voltage standard of the DDR3 SDRAM and the CPU_RESETN line. According to the schematic, these two wire sets (on the same bank) are at 1.5V. According to the master XDC file, however, the CPU_RESETN line is listed as 1.2V. According to the board definition file, the DDR3 lines are 1.5V's. Can you tell me which is is? Thanks! Dan
  6. Turn your Nexys Video board into something useful for hardware development by adding the IO capabilities of another FPGA board. In this project the other board is a Digilent Spartan 3A Starter board. But it has a lot of resources that make it useful for a variety of projects needing an FPGA. The "magic" is supplied by those wonderful Ethernet PHY modems. Release 3 offers two target boards, Gigabit and 100 Mbps designs. Check it out even if all you want to do is connect any two FPGA boards with Ethernet capability.
  7. Hi everyone, I have started using the Nexys Video board and have a question about DPTI before starting: I understand that when channel A is used in synchronous FT245 mode in the FT2232 chip that channel B is switched off. Is that correct? That would mean I cannout use synchronous DPTI in parallel with Vivado debugging, right? One alternative is using asynchronous mode apparently, but I am also wondering if I could connect my debug cable to the unequipped JTAG port instead? Anyone tried that setup? Cheers, Stefan
  8. I'm using the Nexys Video board, and I followed this tutorial and use JTAG to program it. However, data and program are lost when power is off and I have to re-configure the board. What should I do to have the program launched automatically every time the power is on? Through the tutorial mentioned above, I understand that I need a Quad SPI Flash, should I just follow the section N°5? By the way, once the program is stored, how to modify? If I use a QSPI flash, do I just need to create a new bitstream and repeat the instructions in section n°5?
  9. I've finally broken the back of DisplayPort, and have a 800x600 colour bar picture showing using my Nexys Video. Still a lot of work to go before I get UHD resolutions working and a nice generic interface, but all the low-level base technology stuff is working. I started on August 12th, so it has taken over a solid month of hobby time to get this far! Source is on Github at and some notes are on my Wiki at Currently sits at about 9,000 lines of VHDL... but only needs 610 LUTs and 680 flipflops.
  10. Hello everyone, I'm migrating my ancient project from the Nexys2 to the Nexys Video, in UCF, the Hirose FX2 signals on the Nexys2 were declared as LVTTL I/O standards, while the FMC signals are declared as LVCMOS in the XDC files provided on the Digilent Resource Center. After doing some researches, I know that LVTTL and LVCMOS differ by their input voltages. In the paragraph of Power Supplies in datasheet of the Nexys Video, il mentions " An FPGA design can dynamically change the VADJ voltage to suit a certain FMC mezzanine card or application. Care must be taken to disable the regulator first by bringing "VADJ_EN" low, setting "SET_VADJ(1:0)" and enabling the regulator again. Please note that for proper voltage levels in digital signals connected to VADJ-powered FPGA banks (ex. user push-buttons), the correct I/O standard still needs to be set in the design user constraints (XDC or UCF file). See the schematic and/or the constraints file to determine which signals are in VADJ-powered banks. The provided master UCF and XDC files assume the default VADJ voltage of 1.2V, declaring LVCMOS12 as the I/O standard for these signals." The VADJ power rail requires special attention. It is a programmable voltage rail that powers the FMC mezzanine connector, user push-buttons, switches, XADC Pmod connector, and the FPGA banks connected to these peripherals (banks 15, 16). Dose it mean that if I set the SET_VADJ(1:0) on 11, the VADJ voltage = 3.3V, so the FMC signalss' I/O standards can be set as LVTTL?
  11. Hello everyone, I'm a beginner at Vivado. I am using Vivado 2016.4 and the Nexys Video Board. I've been trying for some days to generate the bitstream for the HDMI-Demo ( But after creating the project with the tcl console I got the error message that some IPs (hdmi_axi_dynclk_0_0, hdmi_rgb2dvi_0_0, hdmi_dvi2rgb_0_0) are locked. So I already upgraded them but now I get the following error messages and have no idea how to solve it. [Synth 8-3302] unable to open file '900p_edid.txt' in 'r' mode [EEPROM_8b.vhd:90] [Synth 8-421] mismatched array sizes in rhs and lhs of assignment [EEPROM_8b.vhd:115] [Synth 8-285] failed synthesizing module 'EEPROM_8b' [EEPROM_8b.vhd:85] [Synth 8-285] failed synthesizing module 'dvi2rgb' [dvi2rgb.vhd:110] [Synth 8-285] failed synthesizing module 'hdmi_dvi2rgb_0_3' [hdmi_dvi2rgb_0_3.vhd:80] [Synth 8-285] failed synthesizing module 'hdmi' [hdmi.vhd:5987] [Synth 8-285] failed synthesizing module 'hdmi_wrapper' [hdmi_wrapper.vhd:49] [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details I already looked at the forum here and consulted google, but found no solution or a similar problem there. Does anyone of you solved this problem already or has an idea how to solve it? I would be very thankful for any kind of idea.
  12. I was attempting to use the Board tab within a block design in Vivado 2016.4 to connect some of the board interfaces on a Nexys Video FPGA board. In particular, the HDMI In component goes and instantiates both the TMDS signals in, as well as the DDC signals out, and Vivado marks the HDMI In component as connected. However, when I go to synthesize or elaborate the design, I get a bunch of messages telling me that top-level ports have not been assigned to an IO, and if I open up the I/O Port window, I can see that there's no package pin assigned to the HDMI ports. The only package pins that seem to be assigned are the board clock and reset. I don't think it's a problem with the board files, since I can clearly see from the Board tab that the interfaces are there. And the tool did know which pins were connected to clock and reset. My concern is that it looks like the iostandard and loc properties in part0_pins.xml aren't being understood by Vivado, since the ports ended up unconnected and some have the wrong IO standard (see screenshots). I would upload the project file, but it looks like its too big for the forum by a few MBs, so I posted some screenshots instead, as well as the board files. Does anyone know what could be wrong? I know a UCF file with LOC constraints will work, but that defeats the whole point of the board files that include pin definitions. mig.prj board.xml part0_pins.xml preset.xml
  13. Hi, The FPGA end of the high speed FIFO is pretty well explained, but I can't find the other side - how do you access the port on the host? It mentions the API, but looking through the API I just can't put one and one together. I've used the old DEPP API before... and although I can find the samples and header files for the DSPI I can't see anything about DPTI in digilent.adept.sdk_2.3.1 Linux SDK. Thanks in advance! Mike
  14. EPI

    Nexys Video Board Heat Sink

    Hi, I made an adapter board for my camera application which connects to FMC on the Nexys Video Board. Unfortunately, the male FMC on the adapter board is soldered in wrong direction, so that the adapter board hangs directly over the Nexys Board and conflicts with the heat sink on it. Is it possible to bend or to cut the plates of the heat sink? Can I remove the heat sink completely? How much would it affect performance? Thanks EP
  15. Masahiko

    Nexys Video

    Hi, All When I preparing two NEXYS VIDEO boards and connecting between the respective boards by DISPLAY PORT cable, is the serial data communication in 3.125Gbps unrelated to the standard of DISPLAY PORT possible? ※ This is a question of the purpose to which a circuit diagram in Display Port part isn't exhibited. Thank you. Masahiko Onoda PALTEK Corporation. Japan.
  16. manu80

    Nexys Video & FT2232

    Hello, I have found some discrepancies between two documents of Nexys Video board (datasheet (2016) & schematics (2014)). In the datasheet there are references to a FT2232 chip for PC-FPGA data transfer (page 13). However this chip is not located in Nexys Video schematics. In addition in the datasheet there are discrepancies of the FT2232 connector: J13 in figure 2 (page 7) and J12 in figure 6 (page14). In the shematics the most similar connector is J15, but it is not wired to FT2232. Please could you clarify the discrepancies? Is the schematic available on the website an updated version? Thank you very much in advance, Best regards, Manuel
  17. Hi, Recently picked up an Analog Discovery 2 and Nexys Video. Very excited! Graduated with a BSEE in 2009. However, I never took a digital design (I did take digital logic) class in college. Looking for a way to get started with FPGA. Any guidance on both Analog Discovery and Nexys Video?
  18. Was thinking of plopping some stuff on this, using a Xilinx MicroBlaze CPU, the Analog Devices DAC which is capable of DSP, along with some other IP sourcery to get nice effects...probably 1080p60 or even 1080p144 (eek, 800MHz RAM speed and Artix-7 limitations) visuals on-screen. Posting this off-topic because I haven't even started on it.
  19. I've finally got my HDMI input project to a point where I have something to show. This little picture makes me really happy: This project does the following actions: Advertise HDMI support over EDID/DCCReceive the TMDS signalsDe-serialize them into 10-bit symbolsAlign the symbols using bitslipsTune the input delays for best receptionConvert the TMDS symbols into data valuesExtract CTL, Aux Data Periods (ADPs) and Video Data Periods (VDPs)Extract Video Infoframes from the ADP dataExtract Audio Samples from the ADP data.Extract Raw Pixels from the VDPsPerform 422 to 444 conversion, if required by video formatPerform YCbCr to RGB conversion, if required by video formatConvert Studio Level RGB to Full Range RGB, if required by video formatConvert Audio smaples to a relative db levelOverlay Audio level meters over the video streamConvert the video stream and sync signals back to TMDS symbolsSerialize them through a 10:1 serialisersTransmit the TMDS.I think that this is an awesome base for any video experimentation. I've even got to the trouble of making a GitHub repo for it: Please feel free to fork and extend.
  20. Hi all, I'm currently working on a project for the Oculus Rift, where I need to generate HDMI ouput. Currently I'm using an rbg2dvi IP block to generate TMDS-output, however, when I assign the correct pins in the constraints file by uncommenting the TDMS_clk and TDMS_Data pins, the implementation gives a critical warning about not knowing the I/O standard TDMS, even though it is specified as that in the default constraints file. I'm also already using the latest board files in Vivado 2016.1 Is there anyone who can help me with this issue? Regards, Niels
  21. I am trying to run a microblaze project on the Nexys video development board. However I am having cable driver issues and thus I am attempting to apply the design using a USB host (using a pendrive). I am able to apply a design with simple vivado hardware designs and that works fine. However I cannot get the sdk code for the microblaze to run. Currently I am using the download.bit file generated by the SDK. This bit file is generated using a bootloop. I am following this tutorial ( and so the design should not be the problem. My question is, should the design work if I use the download.bit file generated by SDK (by pressing program FPGA) or should I be using a different bit file to boot from a pendrive? Thanks.
  22. Hi all, I am planning to use a Nexys Video to process a 3D image of two cameras and send it to an Oculus Rift. However, these cameras (OV5642) require quite a few GPIO pins. As it seems I can use 24 pins for GPIO (8 pins per PMOD header, 3 headers), but I need about 40. Is there an affordable way to get more direct GPIO onto this board? So far I have found nothing but a ridiculously expensive FMC card. Thanks in advance.
  23. Under 200 lines of code. I'll probably optimize it more to reduce LUT/FF count. The core UART component will be on OpenCores.
  24. Hello, I am prototyping a concept on the Nexys Video Board. I would like to use the FMC connector and build my own FMC-like board. I will be using both GTP and SERDES outputs. considering the speeds (2.4Gbps, 300Mbps) I need to make sure signal integrity is up to standards all the way from FPGA Ball to the chip on my FMC board including connectors and co. Therefore I need info on the Nexys Video Layout. could you provide: -full layout so I can do post-layout model extraction for the GTP and SERDES io lines, for simulation with Hyperlynx? or -hyperlynx models of the lines? best regards. toby
  25. I've recently ordered one of the Nexys Video evaluation boards. After reading through the reference manual, and, I've noticed that the project files have not been uploaded yet (as of 7/1/2015). Do we have an estimate date for when it'll be available? Thanks!