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Hello, I have a very simple technical question. In Xilinx xc7a35ticpg236-1L Artix-7 FPGA there have only 20800 LUTs found both manual and vivado tools showing also. But in the layout or floor plan, the number of LUTs is more than 20800. Each LUT in the layout plan can be accessed by changing the location through XDC file. But why all LUTs( which is more than 20800) in the layout could not be implemented at a time. Is there any physical constraint? Thanks in advance. Regards, Foisal