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Showing results for tags 'lattice'.
Hello, this is my first post in this forum. Im working on a project which I should sample data from ADC (ADS5463), and then fft the sampled data and see the results. The sampling clock is 400MHz and my FPGA working with DRY clock coming from the ADC which is 200MHz (fs/2). Im sampling the data with DDR interface using Lattice IP (GDDRX1_RX.SCLK.Aligned Interface), which sampling 12 bit DDR data into a bus of 24 bit (there the 11:0 bits is positive edge data and 23:12 is the negative edge data). Next Im storing this data into 2 FIFOs, one for the positive edge data and another for th
So I have the BeagleWire FPGA cape for the BeagleBone Black and I want to send interrupts from the FPGA to the linux os on the BeagleBone every time a switch on the cape . The BeagleWire consists of the Lattice iCE40HX4K FPGA. I understand this is done through GPIO and that an interrupt request line has to be set up but I need specifics and a better explanation of how to actually code this is Verilog. I'm new to FPGAs, just starting out, so any help would be appreciated. Details regarding the BeagleWire including its open source software, can be found below: https://www.crowdsupply.com/qw
Where are the reference design verilog HDL files for the Diglent PMODAcl adxl345 or adxl362 accelerometers on the latticesemi icestick? they are mentioned in various documents, but I did not find source files nor documentation. I did find Nexys3 & Zedboard
Hi guys, I'm trying to use Reveal in my project but the Reveal Analyzer shows me this error: ERROR: core0 cannot trigger. See Reveal Troubleshooting Guide for more details. Problem cause is sample clock or power off. I don't understand the error message, the board is correctly power on and the clock is working since I use it to turn on/off some leds. Someone can help me? Thanks in advance!