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Found 4 results

  1. Hello, this is my first post in this forum. Im working on a project which I should sample data from ADC (ADS5463), and then fft the sampled data and see the results. The sampling clock is 400MHz and my FPGA working with DRY clock coming from the ADC which is 200MHz (fs/2). Im sampling the data with DDR interface using Lattice IP (GDDRX1_RX.SCLK.Aligned Interface), which sampling 12 bit DDR data into a bus of 24 bit (there the 11:0 bits is positive edge data and 23:12 is the negative edge data). Next Im storing this data into 2 FIFOs, one for the positive edge data and another for the negative edge data. My next step which Im currently working on is to insert this data into the FFT IP module which Lattice provides. (https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=2ahUKEwiBl_HfzovoAhVKY5oKHfNPBt0QFjABegQIAhAB&url=http%3A%2F%2Fwww.latticesemi.com%2Fview_document%3Fdocument_id%3D28236&usg=AOvVaw3HSzLdNneCLsy5wEoUnUOx) I attached timing digrams (timings.pdf). The FFT IP Im creating is 12bit width input/output so I need to time the input flags in a way that it take first data from the positive edge FIFO and the next data from the negative edge FIFO and processing so on in a stream. Of course Im paying attention to all the flags as the IP telling. I want to ask some guidelines questions about how to do it correctly. 1. Do I need a state machine which indicates when the FIFO is full and only then to read the data into the FFT input? Or I can start writing to the FFT without state machine and just counter register which indicate when is read enable asserted and start reading to the FFT? 2. Do I need to fill the FIFO and then read the data until its empty, or I can write to the FIFO and read from the FIFO to the FFT continuously? 3. Any guideline how to make this task correctly? I never did this before.. From my prepective I would just wait for ready flag from the FFT IP and read_enable from the FIFO and start to provide data to the FFT IP but I told the there is more timing managment to be made. thanks. timings.pdf
  2. So I have the BeagleWire FPGA cape for the BeagleBone Black and I want to send interrupts from the FPGA to the linux os on the BeagleBone every time a switch on the cape . The BeagleWire consists of the Lattice iCE40HX4K FPGA. I understand this is done through GPIO and that an interrupt request line has to be set up but I need specifics and a better explanation of how to actually code this is Verilog. I'm new to FPGAs, just starting out, so any help would be appreciated. Details regarding the BeagleWire including its open source software, can be found below: https://www.crowdsupply.com/qwerty-embedded-design/beaglewire https://github.com/pmezydlo/BeagleWire
  3. peepo

    PMOD ACL

    Where are the reference design verilog HDL files for the Diglent PMODAcl adxl345 or adxl362 accelerometers on the latticesemi icestick? they are mentioned in various documents, but I did not find source files nor documentation. I did find Nexys3 & Zedboard
  4. Hi guys, I'm trying to use Reveal in my project but the Reveal Analyzer shows me this error: ERROR: core0 cannot trigger. See Reveal Troubleshooting Guide for more details. Problem cause is sample clock or power off. I don't understand the error message, the board is correctly power on and the clock is working since I use it to turn on/off some leds. Someone can help me? Thanks in advance!