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Found 93 results

  1. Hi, We were using Metaware debugger with Digilent JTAG-HS2 cable HS2 RevA for JTAG connection. When 7 processors are in chain, first processor in the chain is not able to read back the memory into Metaware GUI. We notice that write/read is happening correctly in the design by chipscope debugger. We tried many other processor chain combinations and were able to get the metaware working with 8/9/10/11 processors but not 7 processor chain. Currently we have many such digilent HS2 RevA cables purchased online (Sandisk India Design Centre, Bangalore) and all of them facing the same issue. We have installed the new Adept driver digilent.adept.system_v2.16.4 and still the issue exist. We are suspecting hardware issue in the cable. Let me know if someone from Digilent support could have done a fix?
  2. Any chance of support for JTAG protocol on the Digital Discovery? How about a driver for openocd that could turn the DigitalDiscovery in a jtag host. It could program the fpgas and flash memory, run gdb and collect trace data all from one little box. I am impressed. Is there an academic price ? John Eaton
  3. Hi everyone ! I'd like to use the JTAG-HS3 cable to work on a project which consists in testing several interconnections between devices on a board. I'm using DJTG and DMGR APIs and i'm connected via ssh to the computer which has the cable plugged on. My question is: How do i connect to the board with the DMGR API? I know that i have to use DmgrOpen() function but it requires a "device name", which i don't have. Thanks in advance ! Have a nice day !
  4. Hi, I'm using Digilent's XUP USB-JTAG Programming Cable to program 'Z-turn board' which uses Xilinx Zynq-7000( There was no problem when I programed Bitstream or BBRAM through JTAG, but when I tried to program eFUSE Xilinx Vivado threw an error - ERROR: [Labtools 27-3277] jsn-DLC9LP-00000000000000 cable is not supported for EFUSE programming. Please use a Xilinx PCUSB2 DLC10 or approved Digilent cable I think my cable is approved one. Does anyone have any solution for this? Thank you in advance.
  5. Hi, I'm new to this forum so hopefully this has not been asked already. We have a system that contains an embedded Raspberry Pi 2 board and Xilinx FPGAs. We would like to be able to remotely debug FPGA issues. We have been looking into the Xilinx Virtual Cable (XVC) solution. This would allow us to connect Xilinx debugging tools like Chipscope to our FPGAs over an Ethernet connection. I have seen a few implementations where GPIOs from a Raspberry Pi connected to Xilinx FPGA JTAG signals and XVC server code running on the same Raspberry Pi allow for debugging FPGAs remotely. The code I have seen bit bangs the GPIO pins which seems very inefficient. I was wondering if Digilent has a solution where a Digilent USB to JTAG module is used for the Raspberry Pi to JTAG connection instead of GPIO pins to speed things up. If there was such a solution we would ship something like a JTAG-HS2 with all our systems so we could remotely fix problems at customer sites. Does Digilent have such a solution and if not do they supply Raspberry Pi software APIs that would allow customers to develop such a solution? I took a look at the Adept 2 stuff but that looks like it's targeted at configuring FPGAs. I don't think it's for integrating with Xilinx tools. I also looked at the "Digilent Plugin for Xilinx Tools" but I don't think there is a Raspberry Pi version of the plugin and I'm not sure if the plugin will work with XVC. Thanks in advance. RL
  6. Hello, your user's guide linked below says to use a standard Type-A to Micro-USB cable. What would the effect be using a micro-B cable wired for OTG?
  7. Hi: I am creating a board based on XC7Z010-1CLG400. According to the design requirements, I need to intergrate the USB to JTAG circuit on board to simplify user's work processing. I can not find the circuit on Zybo SCH. But I found these is similar circuit done by FT232HQ and 93LC56BT on Zed sch. Then my questions are: 1) Dose this circuit make sense to XC7Z010-1CLG400? 2) Are these any additional configurations need to be processed on FT232HQ or 93LC56BT? 3) Are these any additional configurations need to be processed on PC side or Vivado side? Tks!
  8. Hi, I just updated all of our test PCs from XP to Windows 7. We were using "Device Programming" from WebPACK_42wp30_full_installer.exe to program our Xilinx XC9500 CPLDs. We use the JTAG3 (Parallel Port) cable to program our devices. It has become apparent to me, i believe, that there is a compatibility issue with this WebPACK version and Windows 7. Does anyone know where I can find the WebPACK that will program our CPLDs using Windows 7? I've been on Xilinx's website and there are too many options, so if you could be as specific as possible I would sincerely appreciate it. Thank you Ryan
  9. Hi, I am working on a unit that has Spartan 6 XC6SLX9 (TGFP144) devices. Each board has 1 Spartan 6 on it and each board is just a copy of the other (briefly, the unit is a 4 channel transmitter and I have each board handling 1 channel - so they are identical copies). I'm trying to find the best way to program these boards in the field remotely (so I can't rely on removing / attaching cables, pushing buttons etc.) One possible solution is to use this: on my motherboard and daisy chain JTAG lines as per Xilinx docs. QUESTION: Can I use the JTAG-SMT2-NC with a full speed USB port (as opposed to a high speed USB port)? The USB hub we use on our motherboard is full speed only. I am not looking for any specific JTAG programming speeds. Second solution I have is to have an SPI flash for each FPGA and have them all on the same "shared" bus (the SPI flashes would be programmed by my uC on the motherboard). Since the FPGAs take control of the SPI bus on configuration, I'd be "de-coupling" the "shared" bus from the per-board bus with a buffer as shown below: So when PROGRAM_B is raised to HIGH, the buffer tri-states its outputs (so the shared bus from other FPGAs is no longer in contention). QUESTION: Thoughts? Does this seem reasonable? I'm slightly leaning towards the first option - it seems more robust since JTAG was made to do the daisy chaining stuff -- but depends on whether full speed will work. Thanks, Aditya
  10. Hi , I have a question with the PMOD . I am using ZYNQ 706 board PMOD ports to connect to my fabric (PL) . I have pin locs in place for the PMOD which is connected to the JTAG singals of the ARC processor. I have attached the board setup. djtgcfg enum. Device: JtagHs2 Product Name: Digilent JTAG-HS2 User Name: JtagHs2 Serial Number: 210249A05F4C Before programming the bit file even with the board turned off. djtgcfg init -d JtagHs2. [piyerlab1]$ djtgcfg init -d JtagHs2 Initializing scan chain... Found 0 device(s): When i turn on the board without bit file. [piyerlab1 ~]$ djtgcfg init -d JtagHs2 --verbose Initializing scan chain... ERROR: failed to initialize scan chain Received error: init failed Again With board turned on and bit file programmed , [piyerlab1]$ djtgcfg init -d JtagHs2 Initializing scan chain... Found 0 device(s): I don't know how debug this. I don't know why my arc jtag chain is not detected. I am connected to the PMOD J58 of the ZYNQ 706 board. This PMOD pin is connected to my ARC processor JTAG pins. Please advice how to debug. Regards, Prashanth
  11. Hi All, I am trying to install digilent driver for the digilent hs2 cable which i have. I want to install the driver on 64 bit red hat machine. I have metaware software which is 32 bit executable. does that mean i should install 32 bit version of digilent cable driver? metaware complains it not finding shared libraries in the runtime. I downloaded the 32 bit version and installed them but still it didn't find those shared libraries. I eventually added these shared libraries to the LD_LIBRARY_PATH to the 32 bit shared library. This is the guide i followed to install and go to downloading and installing digilent driver section. I also installed the digilent utility drivers to test if my jtag device is connected. It says no device. lsusb finds the FTDI chip. How can i make sure i have drivers installed correctly and i have jtag connected? other end of the cable is connected to the FPGA PMOD pins which inturn is connected to the 4 wire jtag pins of ARC processor. Thanks, Prashanth
  12. Hello, I have a Zybo Zynq 7000 board and I would like to know if any of the following debuggers can be used with this board. BusBlaster PICkit 3 MPLAB ICD 3 MPLAB REAL ICE Thanks in advance.
  13. Hi there, I've just started with CPLD design, using the Digilent Coolrunner II CPLD starter board (Rev. 3.0) and successfully synthesized my code with the Xilinx ISE development software. I would now like to integrate a Cmod breadboardable CPLD module into one of my projects. I don't own a programming cable/adapter, so I was wondering if I could use the Starter Board as a programmer via its JTAG interface. Looking at the schematic, I could not find a way to connect a JTAG daisy chain with another external CPLD, because the JTAG signals are all connected in parallel. Would it be possible to simply not power the CPLD on the Starter Board (detatching JP2) and connect the external CPLD to the JTAG pins? Best regards Stefan
  14. Hello everyone... I'm new to this world and I bought a Basys2 a couple of years ago to use in my graduation. But I have never used it again since that time! Now I'm interested in discovering this world a bit more and the JTAG interface! Is it possible to write programs and load them into the FPGA board without having the ISE software?
  15. A customer has asked the following question. Can someone help? "I am designing my own boards and I need a programming that I can plug into a header. I am targeting Coolrunner II XC2C64A CPLDS. What cable would you recommend?"
  16. alex.watson

    JTAG HS3 Header

    I need to select a header to which the JTAG HS3 cable can connect. I don't see a one that is specifically made for the HS3, so I'm just looking for a header with a 2mm pitch, 14 pins total, and 2 rows. Is there any mechanical information available for the HS3? I plan to use a right-angle header, so I need to be sure that there's enough clearance for the connector.
  17. Hi, I'm having a problem programming di EEPROM of the FT2232HQ on my Digilent CMOD A7 35T board with FT_PROG, I hope someone can help. I wanted to change the hardware and the drivers of the A port to UART and VCP respectivly. After that, noticing that I couldn't program the FPGA with Vivado anymore, I re-programmed the FTDI with FT_PROG to its initial state (port A with 245FIFO hardware and D2XX Direct drivers), but I'm still not able to program the FPGA with Vivado because it seems to not recognize any hardware target. It seems that the FTDI is not able to connect to and to control the JTAG circuitry anymore. I must say that first of all I also created a template of the EEPROM in order to have a stable state to which return in any case.Isn't there a way to program the FTDI to its inital (factory) state?
  18. Hi, I have just received a CMOS S6 evaluation board (410-282P-KIT). Before I program it with my development code I wanted to verify my setup is working Ok. I am using Xilinx 14.7 on a Windows 7 PC. I have loaded iMPACT and successfully initialised the scan chain. I assigned the demo bit file to the FPGA and the demo mcs file to the flash device. When I ask it to iMPACT to verify the contents of the flash memory it fails at address 0. The iMPACT console output is displayed below. INFO:iMPACT - Current time: 11/07/2016 13:18:16 PROGRESS_START - Starting Operation. Maximum TCK operating frequency for this device chain: 25000000. Validating chain... Boundary-scan chain validated successfully. '1': IDCODE is '012018' (in hex). '1': ID Check passed. '1': IDCODE is '012018' (in hex). '1': ID Check passed. '1': Reading device contents... Failed at address, 0 '1': Verification Terminated PROGRESS_END - End Operation. Elapsed time = 1 sec. Is it possible to verify the PROM contents and if so what am I doing wrong? Regards, Stewart.
  19. Hi, Is it possible to program the JTAG-USB cable directly via the FTDI D2XX library, bypassing the Adept DJTG library? It seems to be possible to identify the device after a call to FT_SetVIDPID, but FT_OpenEx always seems to return FT_DEVICE_NOT_OPENED. Is another step needed first? Or is the source code for the Adept SDK libs available? Thanks, Jon
  20. Hi all, I wondered if anyone could help. I'm trying to program up the Arty board on Ubuntu 14.04 running in a virtualbox on Windows 10. I can get the board to program up through Windows directly, but not via the Ubuntu virtual machine. I get the following debug info: May 15 18:36:36 simon-VirtualBox kernel: [10042.685578] usb 1-1: new high-speed USB device number 11 using ehci-pci May 15 18:36:37 simon-VirtualBox kernel: [10043.014001] usb 1-1: New USB device found, idVendor=0403, idProduct=6010 May 15 18:36:37 simon-VirtualBox kernel: [10043.014005] usb 1-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3 May 15 18:36:37 simon-VirtualBox kernel: [10043.014007] usb 1-1: Product: Digilent USB Device May 15 18:36:37 simon-VirtualBox kernel: [10043.014009] usb 1-1: Manufacturer: Digilent May 15 18:36:37 simon-VirtualBox kernel: [10043.014011] usb 1-1: SerialNumber: 210319789722 May 15 18:36:37 simon-VirtualBox kernel: [10043.021237] ftdi_sio 1-1:1.0: FTDI USB Serial Device converter detected May 15 18:36:37 simon-VirtualBox kernel: [10043.021267] usb 1-1: Detected FT2232H May 15 18:36:37 simon-VirtualBox kernel: [10043.026035] usb 1-1: FTDI USB Serial Device converter now attached to ttyUSB0 May 15 18:36:37 simon-VirtualBox kernel: [10043.031707] ftdi_sio 1-1:1.1: FTDI USB Serial Device converter detected May 15 18:36:37 simon-VirtualBox kernel: [10043.031807] usb 1-1: Detected FT2232H May 15 18:36:37 simon-VirtualBox kernel: [10043.037573] usb 1-1: FTDI USB Serial Device converter now attached to ttyUSB1 May 15 18:36:37 simon-VirtualBox mtp-probe: checking bus 1, device 11: "/sys/devices/pci0000:00/0000:00:0b.0/usb1/1-1" May 15 18:36:37 simon-VirtualBox mtp-probe: bus: 1, device: 11 was not an MTP device but try as I might - I can't get the hardware manager to pick up the JTAG. I'm wondering if it something to do with the last eror? Any help would be greatly appreciated. Many thanks, Simon
  21. Has anybody used one of the USB over CAT5/6 extenders with a Digilent JTAG programming cable? Something like this: We're trying to program devices that are either in different rooms or across the room from the programming computer. The main concern is that USB may not be able to supply enough power for both adapters and the JTAG device. Thanks, Will
  22. Hi. cant program xcf04s with jtag-hs1 rev.a, adept says: ===== Digilent Adept ===== Adept System Rev 2.7 Adept Runtime Rev 2.16 Adept Application Rev 2.4.2 Copyright © 2010 Loading board information... Warning: Could not find specific board information Initializing Scan Chain... Default information loaded. Found device ID: d5c66093 Initialization Complete. Device 1: UNKNOWN cpld unknown. but the same cable works alright with xcf02s. also jtag-usb works ok with this xcf04s
  23. Hi all, I want to know the detail dimension of JTAG-USB cable connector header pin. I know this is very common header pin connector, but I want to understand its pin length and width to ensure the connection. Does anyone know about this? Thank you!
  24. imaviet

    JTAG SMT1 vs. SMT2

    Hello, I am looking to replace the JTAG SMT1 programming module on a VC701 evaluation board with a Virtex 7 FPGA due to a bad micro USB connector. The JTAG SMT1 module is not in stock anymore, and I was wondering if JTAG SMT2 would be compatible with the eval board I am using. The difference between the two modules are SMT2 has GPIO. The rest of the JTAG port connections are identical. Since I will not be using the GPIO, is it ok to leave these pins floating? Thank you for your help. VC701 JTAG SMT1 Module,395,923&Prod=JTAG-SMT1 JTAG SMT2 Module,395,1053&Prod=JTAG-SMT2
  25. When I updated the FTDI VCP drivers( ,win7 X64 2.12.10), the ARTY onboard JTAG disappeared. And there are two USB-TO-COM on my computer. See attachment, please. Any suggestions?