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Found 15 results

  1. Hi, We would like to synchronize the DD clock with an external clock and use an external trigger for starting the acquisition. Using the sync mode, we haven't managed to do so for acquiring I2S data. In our set-up, the external signal clock is connected to one input of the DD (DIN15). The external clock signal connected to DIN15 is externally triggered. In the logic, we chose the Sync mode and specified this input channel (DIN15) as the clock beside the other channels used by I2S data. And then the pattern is triggered by the logic. With that set-up, the pattern will start running w
  2. I'm designing an application using the Audio CODEC of the Zybo Z7. I'm configuring the CODEC by I2C properly and could see data coming from the I2S. Then I realized that each time I programmed the FPGA, the Led 5 of the board was turning ON... even this LED is not at all part of my design!! Never mentioned in my constraints and never mentioned in the verilog wrapper. Then proceeding by elimination when analyzing the constraints, I realized that this LED was turned ON as soon as the I2S clock went enabled... with below constraints: NO LED TURNED ON ##I2S Audio Codec ##set
  3. Good day wizards, I've tried to introduce myself here, but now I would like to ask for a comment on my thoughts. My goal is to master audio processing (mainly routing and level controls for a beginning) on FPGA. The diagram will be very simple: Audio signal generator => ADC => FPGA => DAC => Analyzer (Spectrum, THD, Level) Audio signal generator will be made of two NE555 clocks with different frequencies (say 1kHz and 15kHz) to have a difference between L and R channels. ADC will be CS5381 ([email protected]), I2S output. DAC will be CS4390 ([email protected]),
  4. Hello everyone! I am broadcast audio engineer (ex Harman Pro/Studer) with decent experience of complex audio/control systems and DIY enthusiast with Arduino and Raspberry type-of-toy knowledge:) I also can code PHP (Yii/Laravel), a bit of Python and .NET (WPF, Core and Web Forms). Component level repairs were more of a childhood game, but smell of flux was always somewhere near.. This time i have a goal to get familiar with FPGA world, so here I am and immediately starting a new thread regarding my project:) Cheers!
  5. I am trying to interface a MEMS microphone ICS-52000 with the Digital Discovery board. The microphone outputs data using Time Domain Multiplexed (TDM) signaling. TDM is somewhat similar to I2S but without the left and right channel. The Digital Discovery board has I2S listed under Logic. I want to make a Protocol for TDM. Is it possible to use the Digital Discovery board to develop a protocol that will generate a clock signal (output) along with a word select (output) synchronous to the clock signal and then read data (input) from a connected microphone? Data would be streamed to a file.
  6. I am doing a project with some audio DSP. For this I am using the audio codec on the Zybo. The first thing I want to do, is to be able to record and playback audio with a little delay between input and output. In order to speed up the development process, I decided to use the DMA Audio demo. But I'm lacking some information or rather some documentation. So is there any of your guys who knows which registers is references to here (Audio controller registers) in the code below. Since I2S is an hardware interface standard, so there should not be any registers. So I think it has something to do wi
  7. I am currently trying to setup the ssm2603 audio codex on the zybo board to output audio, with a purely rtl design. I am having issues setting up the audio codex via i2c. I am wondering about how you should send the address information to the audio codex to initialize the setup registers. Below is an RTL state machine of how I am trying to write the register values to the codex. Can someone verify that this is the correct way to address the registers? I am unable to get anything out from the audio codex currently, and I don't think my initialization is working. always @(*) be
  8. Hello All, I tried the program given in but there is no output on the SD. I have simulated the clock with 100MHz and got these values. clk 10ns 100Mhz Sclk 1.56Mhz mclk 40ns 25Mhz SD is always zero in-spite of setting the input data_l and data_r as Ones as shown in picture and simulation output files. I am unable to find the cause for the problem. Am i missing anything in testbench code, as I am simulating only CLK ? What changes are to be made in that code if i have to use internal SCLK. I have a
  9. lukap

    I2S IP core and AXI DMA

    Hello. I'm doing a sound analyzing project on the Zybo board and I'm having hard time using the AXI DMA for transferring data from the I2S controller to RAM. I'm using the I2S controller from the Digilent's github. I am trying to do the data transferring "properly" with a DMA and as there are no PL330 examples to be found (at least not bare metal, which is what I'm doing), I'm trying to use the AXI DMA. However I can only get a few samples to the RAM. I don't really know if there's a problem in the I2S controller or in my configuration of the DMA, so I'd first like to know if I underst
  10. After trying about everything I could think of, I am still not able to produce any sound through the DAC on the Zybo's audio chip. I tried initializing the chip via I2C using what I think are the proper register values and the proper power on sequence, both using a core I wrote myself, and alternatively by connecting the I2C interface through to the Processing System and using Linux and i2c-tools there to set the register values from the command line. My initialization sequence includes activating the digital core (R9), enabling the DAC by setting DACSEL, unmuting the DAC, powering on bot
  11. Hello, I receive my I2C Audio PMOD ( today and I want to use it with my ZYBO. My I2S transmitter look like this: library ieee; use ieee.std_logic_1164.all; entity I2S_Transmitter is generic ( DATA_WIDTH : integer := 32 ); port ( Clock : in STD_LOGIC; MCLK : out STD_LOGIC; Data_In : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); LRCLK : Out STD_LOGIC; DOUT : out STD_LOGIC; Reset : in STD_LOGIC; Empty : out STD_LOGIC
  12. Hello guys; Can you refer me to a quick guide about how to use Audio signal on ZYbo board? I just want to know if there is any simple tutorial about how to get data from audio jack and have in on Arm side. Appreciate your comments in advance.
  13. I trying to use the PmodI2S for the first time, but am unable to get sound from the port. I read thru the post "Pmodi2s Stereo Output Pmod - How Can I Get This Thing To Work?", but unfortunately it didn't solve my issue. I'm sending I2S audio to the pmodI2S module with a PIC32. The PIC32 is toggling the MCLK pin at 8.3 MHz (I've also tried 11 MHz). Here are the frequencies on the pins, verified with a scope: - MCLK (pin 1): 8.3 MHz (Supplied by PIC32) - LRCK (pin 2): ~31.45 kHz (2x channels) - SCK (pin 3): 2 MHz (I've tried it with the PIC32 supplying this and without
  14. JGRMSL

    I2S L1

    I am working on a DIY project and I accidently used a heat gun to unsolder L1 on my PMOD I2C board I looked at the schematic but do not understand what the L1 part is with the 2500 designation. Some sort of choke filter? I was wondering if anyone could point me in the right direction on replacing this part. Thanks!!!
  15. I got this question from a customer: I have been playing with the raspberry pi and its I2S sound output I have noted the I2C interpreter, but to support I2S you need as second clock signal the LRCLK. This splits the data channel between the left and right information, at the moment using the SPI I can only see one channel based on the “select” input. Do you have any plans to update the software and maybe add I2S support? Is there a way to add I2S functionality via a third party API into the DWF software? Is there a 64 bit version on the way?