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Found 11 results

  1. I am trying to use a DAQ to analyze I2C, SPI, and UART signals and then classify them, so they have to be the actual output signals from the Cora Z7 board. However, I am limited due to the project itself to use only the General Purpose I/O pins (IO0-IOA(IO42)). Is it possible to funnel the SPI, I2C, and UARt signals through these pins, or can you only use the specified pins, such as SDA/SCL, MISO/MOSI, or the USB UART bridge to do this?
  2. Hi all, We are looking to use the Arty board for first tests on a machine vision system we are developing, which runs a 72 MHz parallel interface. For ease of testing I was planning to use the Arty board and its I/Os, but I see that it has 200 Ohm series resistors on each pin which will put a limit on the max allowed switching speed. Are there any specifications on the pins when it comes to speed? With 200 Ohms about 5-8 pF is maximum allowed after the resistor for a 72 MHz signal. Else, as I do not have the board yet, are the resistors easy to get to (silkscreen designators for correct identification) to replace the resistors manually with a lower value? Thank you for your time!
  3. cole12345

    PYNQ-Z1 Capabilities

    Hi all, My group and I are brand new to FPGAs, none of us have any expertise whatsoever. As such, we have a few questions about the capabilities of the PYNQ-Z1 board that some of you seasoned experts can help us out with. First: we will have a TTL (3.3 V) pulse sent to the board which is about ~10 ns long. Can the board detect such a pulse from something like a rising or falling edge? We hope to send this pulse via BNC connection - where could we input this on the board? Second: We also need to output a pulse via BNC connection. Where would this pulse be outputted from? Third: Given the first two questions, should we invest in the following two items? i. https://store.digilentinc.com/pmod-cable-kit-6-pin/ ii. https://store.digilentinc.com/bnc-adapter-for-analog-discovery/ Sorry if these questions seem hopelessly basic. We are new to this type of hardware and would greatly appreciate any help you all could send our way.
  4. Hi, I have a couple of your Wi-Fire RevB modules - excellent boards so far !!. I have done very little with them yet - waiting for Microchips Harmony to 'settle' - its now usable - at V1.03.01 ;-). I have a basic config in and at least running - I can send data out of UART ports so far. So - I now started mapping the IO pins so that I can add my own chips on an add-on board, and the first problem I hit is trying to map your on-board SDCARD :-(. Your spec says that I can drive it with an SPI - which is what I want to do, BUT it also says that SDI3 needs to be connected to pin C4 (CPU pin 9). BUT - this is NOT a remappable pin for this CPU, which can be allocated to SPI3 :-(. I assume that you will fix this in a Rev C board soon ????. If so - what pin will you allocate - so that I can cut & strap my board accordingly - and also avoid using this pin for any other interface :-O. NB I am trying to create a manufacturable 'product' for a client using this module and an add-on board (for custom hardware extension). Many Thanks - hopefully ;-). Best Regards Graham
  5. How to use digilent sparten3E kit for implementation of code generated by system generater? i.e how to use adc dac for giving input and taking output from dac?
  6. Hello, I have a ChipKit Uno rev C with Basic I/O board. I am using MPIDE 20140821. I’m having problems running the IOShield_EEPROM_Demo. I have installed the necessary ChipKit I/O drivers. I have ensured JP6 and 8 are configured correctly on the uno board. The program crashes when reaches the line : IOShieldEEPROM.writeString(0,"ABCDEFGHIJKLMNOPQRSTUVWXYZ"); I have read about this problem on ChipKit online forum, but it does not appear to have been resolved. Would anyone please help. :-) Many thanks Andy
  7. zygot

    Adept SDK

    The documentation for using the SDK software libraries and sample HDL is, let's go with sparse to be kind. I've been using it for a few years but my last project has resulted in unexpected behaviour. I have a design that uses both dpmiref and stmctrl sample HDL components and want to access both in my PC application. I don't get any errors, but when I execute DeppDisable() and then DstmEnable() I sometimes have the contents of epp registers lost. Then, when I try and do a DstmIOEX() transfer UsbStmen never gets asserted and the application hangs until the library code times out. I've done this in the past with success but just am not finding what's different in the current project that is causing me grief. Does Digilent have any useful examples (HDL and C code) using both synchronous an asynchronous USB data transfers in one design? Also, can I really do overlapped synchronous IO? The API suggests yes, the documentation and my experimentation no.
  8. Mendeln

    Zybo Board : Pmod to I/O

    Hello everyone, I would like to use all I/O from Pmod connectors (6x8, 48 I/O) but I am not sure that's possible. Actually, I am wondering if we can program the FPGA in order to have 8 single-ended signals for High-Speed Pmods. I think it can work like this. However, the crosstalk issue is mentionned in the reference manual and I don't know how far it can work without problem. Otherwise, I am not focused only on that board. I am looking for one which is able to handle a screen, a mouse, a keyboard, a printer and 45-50 digital I/O in order to make an embedded computer. If someone has any suggestion, I would appreciate. Thanks Mendeln
  9. I am trying to use older PAL devices with a Vcc requirement of 5 V on the EE . When using a Switch or Push Button in the Static I/O Module, the output levels are: HIGH: 3.3 V LOW: 1.6 V The low level is obviously too high. Is EE's Static I/O not intended for 5 V?
  10. Hello, I'm trying to follow the tutorial posted here: https://reference.digilentinc.com/nexys4-ddr:gsmb I got as far as "Generating Bit File" step. This step fails with the following message in the console: ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 1 out of 50 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: sys_clock.ERROR: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 1 out of 50 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: sys_clock. It seems I'm missing some configuration commands which normally go in the *.xdc file, but the tutorial did not specify that an *.xdc file is needed. I'm running Vivado 2014.4 and the board is PB200-292, rev C. Has anybody seen this before?
  11. I'm trying to use Adept I/O Expansion on an Atlys board. I'm following the Adept Software Advanced tutorial (substituting AtlysGeneral.ucf) and all seems well until I attempt to start the I/O connection in the Adept I/O Ex tab. Preparing to program XC6SLX45... Programming... Verifying programming of device... Programming Successful. Warning: I/O Ex Status register not implemented. I'm nost sure where the I/O Ex status register is being called from. Has anyone gotten the extended I/O to work on Atlys? Any clue what I'm missing if I followed the tutorial as it is? Thanks Much,